万兆IPSec协议芯片关键技术研究  

The Key Techniques Research of 10 Gbps IPSec Protocol Chip

作　　者：桂祚勤[1] 崔广财 林存花 陈浩涓 Gui Zuoqin;Cui Guangcai;Lin Cunhua;Chen Haojuan(Jiangnan Institute of Computing Technology,Wuxi,Jiangsu 214000)

机构地区：[1]江南计算技术研究所

出　　处：《信息安全研究》2020年第2期145-150,共6页Journal of Information Security Research

摘　　要：随着网络安全问题日益严重,IPSec安全协议得到了更广泛的应用.采用软件实现IPSec安全协议具有安全性较低、性能不高等特点,而纯硬件实现IPSec安全协议具有灵活性较差、并行性不高等特点.因此,在深入研究IPSec安全协议的基础上,提出一种采用专用指令集处理器结合硬件加速来实现IPSec安全协议的架构,并采用40 nm CMOS工艺对该架构进行了实现验证,该芯片的IPSec处理性能可达到10 Gbps.With the increasing problem of network security,IPSec protocol has been widely used in many areas.Software implementation of IPSec security protocol has the characteristics of poor security,poor platform adaptability and low performance.Hardware implementation of IPSec security protocol is characterized by poor flexibility and low parallelism.Therefore,this paper based on the analyses of IPSec protocol,proposes a method of implementing of IPSec protocol in combination with ASIP and software.The design of 10 Gbps IPSec protocol chip using 40 nm CMOS process for hardware implantation which performance up to 10 Gbps.

关 键 词：网络安全 IPSEC 专用指令集处理器 抗重放 硬件查找算法 

分 类 号：TP309[自动化与计算机技术—计算机系统结构]