基于脉动阵列的卷积计算模块硬件设计  

Hardware design of convolution calculation module based on systolic array

作　　者：王春林 谭克俊[1] Wang Chunlin;Tan Kejun(Information Science and Technology College,Dalian Maritime University,Dalian 116026,China)

机构地区：[1]大连海事大学信息科学技术学院

出　　处：《电子技术应用》2020年第1期57-61,共5页Application of Electronic Technique

摘　　要：针对FPGA实现卷积神经网络中卷积计算的过程中,高并行度带来长广播、多扇入/扇出的数据通路问题,采用脉动阵列来实现卷积神经网络中卷积计算模块,将权重固定到每个处理单元中,并按照输入和输出特征图的维度来设置脉动阵列的大小,最后通过Vivado高层次综合实现卷积计算模块的硬件设计。实验结果表明,本设计在实现1级流水化时序要求的同时,具有较低的资源占用和良好的扩展性。Aiming at the long broadcast, much fan in/fan out data path problem brought by high parullelism in the process of the Field Programmable Gate Array(FPGA) to realize the convolution computation in convolutional neural network, this paper adopts pulse array to realize convolution calculation module of convolutional neural network, fixes weights to each processing unit, according to the dimension of the input and output characteristic figure sets to pulse array size, and finally by Vivado high level synthesis real-izes convolution calculation module hardware design. The experimental results show that the design has low resource occupancy and good expansibility while realizing the time-series requirements of level 1 pipelining.

关 键 词：FPGA 脉动阵列 卷积计算 高层次综合 

分 类 号：TN402[电子电信—微电子学与固体电子学] TP391.41[自动化与计算机技术—计算机应用技术]