基于国产FPGA的千兆以太网交换机复位系统设计  

Design of Reset System Based on Domestic FPGA for Gigabit Ethernet Switch

作　　者：王立莹[1] 左延智[2] WANG Liying;ZUO Yanzhi(The 54th Research Institute of CETC,Shijiazhuang 050081,China;Beijing Institute of Tracing and Telecommunication Technology,Beijing 100094,China)

机构地区：[1]中国电子科技集团公司第五十四研究所,河北石家庄050081 [2]北京跟踪与通信技术研究所,北京100094

出　　处：《无线电工程》2020年第3期253-256,共4页Radio Engineering

基　　金：国家重点研发计划基金资助项目(2017YFB0803201)~~

摘　　要：针对以太网交换设备的国产化需求,研究了千兆以太网交换机复位系统的实现原理,分析了以太网交换机复位系统软硬件设计的实现过程,提出了千兆以太网交换机的复位设计方案,并给出了一种基于国产FPGA的千兆以太网交换机复位系统,通过软件对FPGA复位程序进行了仿真。仿真结果表明,该设计符合千兆以太网交换机的复位时序要求,能满足国产化千兆以太网交换机的设计需求。To address the domestic demand for Ethernet switch,a reset system for gigabit Ethernet switch is studied,the implementation for the reset system with software and hardware is analyzed,and a reset scheme for gigabit Ethernet switch is proposed.Finally,a reset system based on domestic FPGA for gigabit Ethernet switch is designed.The code for FPGA is simulated with software,and the simulation results indicate that the design meets the timing sequence requirements for gigabit Ethernet switch,which meets the expected design requirements for domestic gigabit Ethernet switch.

关 键 词：千兆以太网 复位系统 FPGA 交换机 

分 类 号：TN919.21[电子电信—通信与信息系统]