基于同步异构DSP的CLA模块的脉冲均分算法研究  

Pulse uniformization algorithm of CLA module based on synchronous heterogeneous DSP

作　　者：梁磊磊 何高清 LIANG Lei-lei;HE Gao-qing(School of Mechanical Engineering,Hefei University of Technology,Hefei 230009,China)

机构地区：[1]合肥工业大学机械工程学院

出　　处：《机电工程》2020年第2期191-195,共5页Journal of Mechanical & Electrical Engineering

基　　金：合肥市远大轴承锻造有限公司项目(W2016JSKF0039)

摘　　要：针对数控系统中精插补器输出脉冲分布不均匀的问题,对精插补器的运行机制、硬件结构与软件算法进行了研究,对精插补器的传统解决方案与输出脉冲分布不均匀的原因进行了归纳,提出了一种基于同步异构数字信号处理器(DSP)的控制律加速器(CLA)模块的脉冲均分算法。以使用相同时钟信号、数据总线与指令总线的DSP与CLA为硬件构架,采用并行处理任务、硬件触发CLA程序的模式,使用改进的双脉冲周期插补算法,构建了能够输出分布均匀的脉冲的精插补器;使用TMS320F28377S为硬件平台,利用其在线调试功能,对该脉冲均分算法进行了测试。实验结果表明:在数控系统的循环调度周期中,该设计方案输出脉冲的时间可以达到100%,脉冲周期最短可以达到2μs;该脉冲均分算法可以实现输出脉冲分布的均匀化。Aiming at the problem of uneven distribution of output pulse by the fine interpolation in the numerical control system,experimental study on the operation mechanism、hardware structure and software algorithm of the fine interpolator were summarized,the traditional solution of the fine interpolator and the reason about uneven distribution of output pulse were comparatively analyzed.A method of pulse uniformization algorithm based on the control law accelerator(CLA)module of synchronous digital signal processor(DSP)was proposed.A fine interpolator that could output distributed pulse evenly was constructed based on the hardware architecture with DSP and CLA in same clock signal,data bus and instruction,the running mode of processing task in parallel with running program in CLA by hardware trigger and the improved algorithm of double pulse period interpolation.A method was presented to test the pulse uniformization algorithm by hardware platform with TMS320F28377S and its online debugging function.The experimental results indicate that the time of output pulse occupy 100%of loop scheduling period in the CNC system by the design,and the pulse period can be as short as 2μs,achieve the uniformization of distribution about output pulse.

关 键 词：数字信号处理器 控制律加速器 脉冲均分算法 精插补器 

分 类 号：TH-39[机械工程] TP368.2[自动化与计算机技术—计算机系统结构]