基于CoreConnect总线的DMA控制器设计  

DMA Controller Design Based on CoreConnect Bus

作　　者：吴思博 于宗光 Wu Sibo;Yu Zongguang(School of Internet of Things Engineering,Jiangnan University,Wuxi 214122,China;The 58^th Research Institute,CETC,Wuxi 214005,China)

机构地区：[1]江南大学物联网工程学院,江苏无锡214122 [2]中国电子科技集团公司第五十八研究所,江苏无锡214005

出　　处：《半导体技术》2020年第1期31-36,共6页Semiconductor Technology

基　　金：国家自然科学基金资助项目(61704161)

摘　　要：随着片上系统(SOC)规模的不断增大,各外部设备之间大量数据的交互问题成为芯片系统提高性能的瓶颈。提出了一种基于CoreConnect总线架构的直接内存存取(DMA)高速数据传输系统设计方法,并给出了一种较为完善的DMA控制器设计方案。根据DMA在数据传输应用中的特性,减小了外部设备之间数据大量交互对CPU产生的负担,同时解决了处理器内部总线(PLB)上128 bit数据与片上外围总线(OPB)上32 bit数据之间的传输问题,实现PLB与OPB上外部设备之间数据的双向传输。最后给出了相应的功能仿真结果与现场可编程门阵列(FPGA)验证结果。With the increasing scale of system on chip(SOC),the large amounts of data interaction between peripherals becomes the bottleneck of chip system improvement.A design method for direct memory access(DMA)high-speed data transmission system based on CoreConnect bus architecture was proposed,and a relatively perfect DMA controller design scheme was presented.According to the characteristics of DMA in data transmission application,the burden of large amount of data interaction between peripherals on CPU was reduced,the transmission problem between 128 bit data on process local bus(PLB)and 32 bit data on on-chip peripheral bus(OPB)was solved,and the bidirectional data transmission between PLB and peripherals on OPB was realized.Finally,the corresponding functional simulation results and field programmable gate array(FPGA)verification results were given.

关 键 词：片上系统(SOC) 直接内存存取(DMA)控制器 CoreConnect总线架构 多通道 数据传输 

分 类 号：TN402[电子电信—微电子学与固体电子学]