多优先级通用路由仲裁器的设计实现  

Design and Implementation of Multi-priority Universal Route Arbitrator

作　　者：周刚华 邹德财[1,2,4] 卢晓春 ZHOU Gang-hua;ZOU De-cai;LU Xiao-chun(National Time Service Center,CAS,Xi'an 710600,China;Key Laboratory of Precision Navigation,Positioning and Timing Technology,CAS,Xi'an 710600,China;University of Chinese Academy of Sciences,Beijing 100049,China;School of Astronomy and Space Science,University of Chinese Academy of Sciences,Beijing 101048,China)

机构地区：[1]中国科学院国家授时中心,西安710600 [2]中国科学院精密导航定位与定时技术重点实验室,西安710600 [3]中国科学院大学,北京100049 [4]中国科学院大学天文与空间科学学院,北京101048

出　　处：《小型微型计算机系统》2020年第3期593-597,共5页Journal of Chinese Computer Systems

基　　金：军委科技委科技创新特区支持项目(00100504)资助.

摘　　要：随着芯片工艺的不断发展和多核技术的广泛应用,片上网络上实现路由功能的系统占比越来越高,为更好地处理片上路由系统中多路由多模块同时请求仲裁的情况,本文设计实现两种适用于大多数片上网络结构的多优先级通用仲裁器,通过改善仲裁器的结构,来优化仲裁器的各项性能指标.仿真结果表明:多优先级仲裁器与单优先级仲裁器相比在硬件资源占用、最大工作频率、最大输出时延等方面均得到一定程度的优化.With the development of chip technology and the wide application of multi-core technology,the proportion of systems implementing routing functions on the network-on-chip is getting higher and higher. In order to better handle multi-route and multi-module simultaneous arbitration in the on-chip routing system,this paper is designed to implement two multi-priority general arbiter for most network-on-chip structures. The arbitrator’s specifications are optimized by improving the structure of the arbiter. The simulation results show that the multi-priority arbiter is optimized to a certain extent in terms of hardware resource occupation,maximum operating frequency and maximum output delay.

关 键 词：片上网络 路由仲裁器 可轮循 多优先级 

分 类 号：TN492[电子电信—微电子学与固体电子学]