嵌入式系统中基于FPGA的中频数字接收机的设计  

Design of IF digital receiver based on FPGA in embedded system

作　　者：章森 王锋(指导)[1] 赵河明[1] 彭志凌[1] Zhang Sen;Wang Feng;Zhao Heming;Peng Zhiling(School of Mechanical and Electrical Engineering,North University of China,Taiyuan 030051,China)

机构地区：[1]中北大学机电工程学院,山西太原030051

出　　处：《现代科学仪器》2019年第5期14-17,共4页Modern Scientific Instruments

摘　　要：FPGA是一项智能技术和算法结合的学科,随着新产品的不断推出,开发工具也相对更新很快,关于FPGA的嵌入式研究也越来越多。本文主要针对中频数字接收机系统进行设计,实现了在中频数字信号输出信号速度为2.56Mbps,带宽为1.6MHz。本文通过接收机系统结构设计、数字信号处理模块设计、采样频率设定和系统采样速率的设定来运用vivado平台来编写代码,并用ModelSim进行辅助仿真。FPGA is a subject combining intelligent technology and algorithm.With the continuous introduction of new products,the development tools are relatively updated quickly,and more and more embedded research on FPGA is carried out.This paper mainly focuses on the design of IF digital receiver system.The output signal speed of IF digital signal is 2.56mbps,and the bandwidth is 1.6mhz.This paper uses vivado platform to write code through receiver system structure design,digital signal processing module design,sampling frequency setting and system sampling rate setting,and uses Modelsim for auxiliary simulation.

关 键 词：FPGA 中频 系统 

分 类 号：TP39[自动化与计算机技术—计算机应用技术]