HSRDN: High-Speed Router Design for Various No C Topologies  

作　　者：E.Lakshmi Prasad M.N.Giri Prasad A.R.Reddy 

机构地区：[1]Department of ECE,JNTUACE,Anantapuramu,(AP)-515002,India [2]Department of RRC,MITS,Madanapalle,(AP)-517325,India

出　　处：《Chinese Journal of Electronics》2020年第2期281-290,共10页电子学报（英文版）

基　　金：supported by the MITS(RRC,JNTUA)on behalf of TEQIP-II World Bank Organization。

摘　　要：High-speed router design for network on chip(HSRDN) is proposed for controlling the traffic congestion and deadlocks. Diagonal based nearest-path routing algorithm for No C(DNRAN) can mitigate the effect of latency by opting for the nearest-path to reach the destination in a network and HSRDN is part of DNRAN. When we analyze the performance of DNRAN for all proposed topologies, nearly 50% better in terms of latency reduction and high throughput over existing router architectures. The proposed topologies(2 D-mesh,2 D-Star mesh over regional mesh(SMo RM), 3 D-mesh,and 3 D-torus) are tested with various applications, viz,audio, video and so on. Here, we also tested with cryptography application for DNRAN. When we analyzed the performance of experimental results, exclusively in 2 D-SMo RM nearly 0.6 times latency get reduced, area expanded by 0.25 and 0.33 times throughput increase in 2 D-SMo RM compared with 3 D-mesh and 3 D-torus.Therefore, DNRAN showed an exclusive performance in 2 D-SMo RM compared with other two topologies.High-speed router design for network on chip(HSRDN) is proposed for controlling the traffic congestion and deadlocks. Diagonal based nearest-path routing algorithm for No C(DNRAN) can mitigate the effect of latency by opting for the nearest-path to reach the destination in a network and HSRDN is part of DNRAN. When we analyze the performance of DNRAN for all proposed topologies, nearly 50% better in terms of latency reduction and high throughput over existing router architectures. The proposed topologies(2 D-mesh,2 D-Star mesh over regional mesh(SMo RM), 3 D-mesh,and 3 D-torus) are tested with various applications, viz,audio, video and so on. Here, we also tested with cryptography application for DNRAN. When we analyzed the performance of experimental results, exclusively in 2 D-SMo RM nearly 0.6 times latency get reduced, area expanded by 0.25 and 0.33 times throughput increase in 2 D-SMo RM compared with 3 D-mesh and 3 D-torus.Therefore, DNRAN showed an exclusive performance in 2 D-SMo RM compared with other two topologies.

关 键 词：LOGIC Network on chip(NoC) Virtual channels LATENCY CONGESTION Shortest path routing algorithm 3D-mesh 3D-torus 

分 类 号：TN47[电子电信—微电子学与固体电子学] TN915.05