一种FPGA电路中同步开关噪声的优化设计  

An optimization of simultaneous switching noise problem in circuit design for FPGA

作　　者：杜金艳 DU Jin-yan(Tianjin JinHang Computing Technology Research Institute,Tianjin 300308,China)

机构地区：[1]天津津航计算技术研究所,天津300308

出　　处：《电子设计工程》2020年第6期162-164,169,共4页Electronic Design Engineering

摘　　要：针对某系统在调试过程中,FPGA控制芯片输出数据异常的现象进行了深入分析,发现在访问FPGA过程中,数据线产生同步开关噪声导致DSP不能正常访问;因此,对FPGA芯片的电路设计进行了分析,通过优化电源平面设计,改善电源滤波电容,降低输出驱动能力,提高了FPGA电路设计的可靠性,达到了预期效果。To deeply analysis on a FPGA output data exception of a system can not work properly in the process of testing and debugging.We find that simultaneous switching noise of FPGA output data bus operation of FPGA when the test system can be ccessed by the DSP.Therefore,this thesis discuss the reliability of FPGA integrated circuits and present solutions,Through optimization of the decoupling capacitor and the power supply impedance,and rduce output driving capability.Improve eliability function of accessing FPGA,The proposed method achieves the expected effect.

关 键 词：同步开关噪声 电源滤波 驱动能力 可靠性 

分 类 号：TN47[电子电信—微电子学与固体电子学]