近阈值电压下可容错的一级缓存结构设计  

Design of Fault-tolerant L1 Cache Architecture at Near-threshold Voltage

作　　者：程煜 刘伟[1,2,3] 孙童心[1] 魏志刚[1] 杜薇 CHENG Yu;LIU Wei;SUN Tong-xin;WEI Zhi-gang;DU Wei(School of Computer Science and Technology,Wuhan University of Technology,Wuhan 430070,China;Hubei Key Laboratory of Transportation Internet of Things,Wuhan University of Technology,Wuhan 430070,China;Key Laboratory of Embedded Systems and Service Computing,Ministry of Education,Tongji University,Shanghai 201804,China)

机构地区：[1]武汉理工大学计算机科学与技术学院,武汉430070 [2]交通物联网技术湖北省重点实验室(武汉理工大学),武汉430070 [3]嵌入式系统与服务计算教育部重点实验室(同济大学),上海201804

出　　处：《计算机科学》2020年第4期42-49,共8页Computer Science

基　　金：国家自然科学基金面上项目(61672384);教育部人文社科基金项目(16YJCZH014);中央高校基本科研业务费(2016III028,2017III028-005);嵌入式系统与服务计算教育部重点实验室(同济大学)开放基金(ESSCKF2018-05)。

摘　　要：随着硅的集成度和时钟频率的急剧提升,功耗和散热已成为体系结构设计中的关键挑战。近阈值电压技术是一种能够有效降低处理器能耗的有着广泛应用前景的技术。然而,在近阈值电压下,大量SRAM单元失效,导致一级缓存的错误率升升,给一级缓存的可靠性带来了严峻挑战。目前有很多学者通过牺牲缓存容量或者引入额外的延迟来纠正缓存的错误,但大多方法只能适应SRAM单元的低失效率环境,在高失效率的环境下表现较差。文中提出了一种基于传统6T SRAM的近阈值电压下可容错的一级缓存结构——FTFLC(Fault-Tolerant First-Level Cache),在高失效率的环境下,其表现出了更好的性能。FTFLC采用两级映射机制,利用块映射机制和位纠正机制分别对缓存行中有错的比特位和子数据块进行映射保护。此外,文中还提出了FTFLC初始化算法将两种映射机制结合,提高了可用的缓存容量。最后,使用gem5模拟器,在650 mV电压的高失效率环境下对FTFLC进行仿真实验,将其与3种已有缓存结构10T-Cache,Bit-fix,Correction Prediction进行对比。对比结果表明,FTFLC相比其他的缓存结构,在保持较低面积和能耗开销的同时,拥有至少3.86%的性能提升,且将L1 Cache的容量可用率提升了12.5%。With the aggressive silicon integration and clock frequency increasing,power consumption and heat dissipation have become key challenges in the design of high-performance processors.NTC is emerging as a promising solution to achieve an order of magnitude reduction in energy consumption in future processors.However,reducing the supply voltage to near-threshold level significantly increases the SRAM bit-cell failures,leading to the high error rate in L1 cache.Researchers have proposed techniques either by sacrificing capacity or incurring additional latency to correct the errors in L1 cache.But most schemes can only adapt to the low error rate environment of SRAM bit-cell,and perform poorly in high error rate environment.In this paper,this paper proposed a fault-tolerant First-Level Cache design(FTFLC)based on conventional 6T SRAM cells to solve reliability challenges in high error rate environment.FTFLC adopts a two-level mapping mechanism,which uses block mapping mechanism and bit correction mechanism to protect the faulty bits data in the cache line.In addition,this paper proposed a FTFLC initialization algorithm to improve the available cache capacity by combining two mapping mechanisms.Experimental results show that compared with three existing schemes,FTFLC improves performance by 3.86%and increases 12.5%L1 cache capacity while maintaining a low area and energy consumption.

关 键 词：近阈值电压 一级缓存 容错性 可靠性 低能耗 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]