基于标准DDR总线的内存扩展芯片的设计与实现  

Design and implementation of memory extension chip based on standard DDR bus

作　　者：赵阳洋 陈明宇[1,2,3] 金旭 阮元 张雪琳[1] Zhao Yangyang;Chen Mingyu;Jin Xu;Ruan Yuan;Zhang Xuelin(State Key Laboratory of Computer Architecture,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190;University of Chinese Academy of Sciences,Beijing 100049;Peng Cheng Laboratory,Shenzhen 518055)

机构地区：[1]中国科学院计算技术研究所计算机体系结构国家重点实验室,北京100190 [2]中国科学院大学,北京100049 [3]鹏城实验室,深圳518055

出　　处：《高技术通讯》2020年第3期233-239,共7页Chinese High Technology Letters

基　　金：国家重点研发计划(2017YFB1001602);中国科学院战略性先导专项(XDA06010401)资助项目。

摘　　要：随着计算机领域进入大数据时代,数据的快速增长和以数据为中心的发展趋势给现有的计算机存储带来了机遇和挑战。传统的标准双倍速率(DDR)总线接口采用固定的时序,难以加入各种扩展功能,若引入新型内存器件,则存在时序兼容问题。为此基于现有的DDR协议,本文设计实现了内存缓冲扩展芯片。该芯片与处理器端的物理连接采用标准DDR总线,消除了兼容性问题;并且在芯片逻辑设计中,增加对可变延迟访问和扩展访存指令的支持,为内存增加了智能性,可用于内存加速和内存扩展。本文详细介绍了该芯片采用的关键技术,经过中芯国际40nm工艺流片验证,该芯片逻辑功能正确,运行稳定。在DDR3-1066频率下,该芯片可满足标准DDR3内存读写时序,并在龙芯3A系列主板上顺利启动Linux内核。芯片性能评估结果表明,应用扩展的访存指令可实现访存加速。The rapid growth of data and the trend of data-centric development bring challenges to the existing computer memory system.The traditional double data rate(DDR)bus interface uses fixed timing and suffers difficulty in adding extensions.Moreover,timing compatibility problems are introduced when using new memory devices.Therefore,a memory buffer chip based on existing DDR protocol is designed and implemented.The physical connection between the chip and the processor uses a standard DDR bus,which eliminates compatibility problems.The chip also supports variable delay access and extended memory access instructions.Therefore the intelligence on the memory side is achieved.The chip can be used for memory acceleration and memory expansion.The key technologies of the chip are introduced in details.The SMIC 40nm chip runs stably and correctly.At DDR3-1066 frequency,the chip can meet the standard DDR3 memory read and write timing,and successfully boot the Linux kernel on the Loongson 3A series board.The performance evaluation results show that the application of extended memory access instructions can accelerate memory accesses.

关 键 词：内存缓冲 内存加速 内存扩展 内存智能化 近数据处理 

分 类 号：TP333[自动化与计算机技术—计算机系统结构] TN402[自动化与计算机技术—计算机科学与技术]