基于新型booth选择器和压缩器的乘法器设计  

Design and implementation multiplier based on new booth selector and compressor

作　　者：王佳乐 胡越黎[1,2] WANG Jia-le;HU Yue-li(Microelectronics Research and Development Center,Shanghai University,Shanghai 201900,China;School of Mechanical Engineering and Automation,Shanghai University,Shanghai 201900,China)

机构地区：[1]上海大学微电子研究与开发中心,上海201900 [2]上海大学机电工程与自动化学院,上海201900

出　　处：《微电子学与计算机》2020年第3期5-8,共4页Microelectronics & Computer

摘　　要：为了优化乘法器关键路径延时并减少电路面积,提高乘法器的整体性能.本文在运用基4booth算法的基础上,针对部分积生成器延时相对较大的问题,提出了一种新型的booth选择器,用于提高部分积生成的效率.同时,本文又提出一种新型的4-2部分积压缩器,用于提高部分积压缩器的压缩效率.基于tsmc28nm工艺,对运用上述优化点的有符号16比特乘法器进行仿真验证和综合,本文设计的乘法器关键路径延时为0.98 ns.实验结果表明,本文提出的两点新型设计,能较好的提升乘法器的计算性能.In order to optimize the multiplier critical path delay and reduce the circuit area,improve the overall performance of the multiplier.Based on the Radix 4 booth algorithm,this paper proposes a new type of booth selector for the problem of partial product generator delay,which is used to improve the efficiency of partial product generation.At the same time,this paper proposes a new type of 4-2 partial product compressor to improve the compression efficiency of the partial product compressor.Based on the tsmc 28 nm process,the signed 16-bit multiplier using the above optimization points is simulated and synthesized.The critical path delay of the multiplier designed in this paper is 0.98 ns.The experimental results show that the two new designs proposed in this paper can improve the computational performance of the multiplier.

关 键 词：booth选择器 4-2压缩器 乘法器 部分积 

分 类 号：TN492[电子电信—微电子学与固体电子学]