基于ADC噪声分布的亚皮秒级时钟抖动测试方法  

Sub-picosecond level clock jitter measurement technique based on ADC noise distribution

作　　者：刘洁[1] 王轩[1] 龚科[1] 马伟[1] 周国昌[1] 袁雅婧 LIU Jie;WANG Xuan;GONG Ke;MA Wei;ZHOU Guo-chang;YUAN Ya-jing(Xi'an Institute of Space Radio Technology,Xi'an 710100,China;Xuchang University,Xuchang 461000,China)

机构地区：[1]中国空间技术研究院西安分院,陕西西安710100 [2]许昌学院,河南许昌461000

出　　处：《微电子学与计算机》2020年第3期71-75,82,共6页Microelectronics & Computer

摘　　要：针对时钟抖动与ADC信噪比的关系,提出了一种基于ADC噪底能量分布的亚皮秒级时钟抖动的测试方法.通过建立ADC的采样误差模型,推导出时钟抖动引起的采样误差表达式,分析了时钟抖动造成的采样精度与采样频率上限,剥离出不同频点ADC噪声的成因,从而得到利用双频点采样的时钟亚皮秒级抖动测试方法.并对该方法进行了仿真和测试验证,结果显示GHz以上频率的时钟亚皮秒级抖动测试误差小于10 fs,表明该方法简洁、有效,具有很高的测试精度.For the affection of clock jitter on signal-to-noise ratio(SNR),a novel technique of measuring sub-picosecond level clock jitter based on ADC noise distribution is proposed.By modeling the sampling error of ADC,the mathematical formula of sampling error caused by clock jitter was observed.It also presented the highest frequency of sampled signal limited by SNR.For the different determinant of sampling noise,the measure of sub-picosecond level clock jitter by two frequency sampling was observed.All the conclusions were verified by simulation and test.The results show the test error is less than 10 fS in clock jitter measurement up to a signal frequency of 1.6 GHz,which indicated that the proposed method had a characterization of easy operation and high resolution.

关 键 词：ADC 信噪比 时钟抖动 亚皮秒 

分 类 号：TN792[电子电信—电路与系统]