一种单片高稳振荡器芯片设计  

Design of a high stability oscillator chip

作　　者：谭传武[1] 龚江涛[1] Tan Chuanwu;Gong Jiangtao(Dept,of Communication and Signal,Hunan Railway Professional Technologycollege,Zhuzhou 412001,China)

机构地区：[1]湖南铁道职业技术学院电务技术学院,株洲412001

出　　处：《电子测量技术》2020年第2期73-76,共4页Electronic Measurement Technology

基　　金：湖南省教育厅教育科学研究项目(16B175)资助.

摘　　要：针对传统Pierce振荡器改进了振荡器的起振电路结构,采用负阻起振理论基于0.35μm CMOS工艺设计了一种单片高稳振荡器芯片。芯片主要包含起振电路、缓冲器电路、驱动电路、使能电路及分频器电路,输出频率范围为4 MHz^30 MHz可调,应用cohesion及Hspice软件完成了电路设计与仿真,使用Cadence软件进行了芯片的版图设计,LVS验证后完成了芯片的后仿真工作,仿真结果表明在设定的6种晶体参数下,电路在800μs时完成了起振且在tt、ff、ss 3种模式下输出平稳,该芯片能适用于无线收发信机中。The starting circuit of Pierce oscillator is improved. A single chip high stability oscillator chip is designed based on the negative resistance theory and 0.35 μm CMOS technology. The chip mainly consists of starting circuit, buffer circuit, driving circuit, enabling circuit and frequency divider circuit. The output frequency range is 4 MHz^30 MHz adjustable. The circuit design and simulation are completed by using cohesion and Hspice software. The results show that under the set six crystal parameters, the circuit completes the starting at 800 μs, and the output is stable under three modes of tt, FF and ss. The chip is very special. It is not suitable for wireless charging and wireless communication systems.

关 键 词：振荡器 负阻起振 无线通信 CMOS Pierce 

分 类 号：TN433[电子电信—微电子学与固体电子学]