基于ASIC的并行流水线级联半带滤波器设计  

An ASIC Based Parallel Pipelined Cascade Half Band Filter Design

作　　者：邵杰 万书芹[1] 任凤霞 SHAO Jie;WAN Shuqin;REN Fengxia(The 58th Research Institute,China Electronics Technology Group Corp.,Wuxi,Jiangsu,214035,CHN)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《固体电子学研究与进展》2020年第1期60-65,共6页Research & Progress of SSE

基　　金：国家自然科学基金资助项目(61704161)。

摘　　要：针对高速ADC数字下变频中的实时滤波需求,设计了一种基于ASIC的并行流水线级联半带滤波器。首先根据ADC输出数据速率远高于DSP处理能力的工程问题设计了可以实现16、8、4、2倍抽取的四级级联结构,然后在传统串行滤波器基础上进行了4路并行流水线结构理论推导,该方法降低了运算速度,能够实现高速数据实时处理。在此基础上采用Verilog HDL实现了RTL级描述并采用65 nm CMOS工艺成功流片,仿真和测试结果显示,设计的滤波器能够在保证计算精度的同时实现1 GHz高速采样数据的实时滤波及16、8、4、2倍抽取。A cascade half band filter based on ASIC was presented for real-time filtering require ments in high-speed ADC digital down converter.Firstly,cascade structure with decimation ratio of 16,8,4,2 is designed to meet the engineering challenge where the ADC sample rate is much higher than DSP processing speed.Then,parallel pipelined structure with 4 channels is theoretically derived on the basis of traditional serial filter,and the method reduces the operation speed,which make it pos sible for high-speed data real-time processing.The cascade half band filter is implemented with Veril og HDL RTL-level description and successfully realized with 65 nm CMOS process.Simulation and product test results show that the 1 GHz high-speed input data can be processed in real-time when deci mated by 16,8,4,2 and good calculation accuracy is obtained with the designed filter.

关 键 词：并行结构 流水线 半带滤波器 ASIC 

分 类 号：TN713[电子电信—电路与系统]