一种多接口电平输出频率综合器设计  

Design of a Multi-Interface Level Output Frequency Synthesizer

作　　者：张佳俊 苏淑靖[1] 王少斌 韩文革 ZHANG Jiajun;SU Shujing;WANG Shaobin;HAN Wenge(National Key Laboratory of the Electronic Measurement Technology,North University of China,Taiyuan 030051,China)

机构地区：[1]中北大学电子测试技术重点实验室,太原030051

出　　处：《电子器件》2020年第1期30-33,共4页Chinese Journal of Electron Devices

基　　金：国家自然科学基金项目(51875534);山西省“1331工程”重点学科建设项目。

摘　　要：针对目前不同芯片和设备之间接口电平标准不一样的问题,设计了一种多接口电平输出频率综合器。通过锁相环芯片产生1.6 GHz^3.2 GHz频段的信号,利用并行转串行芯片将锁相环产生的信号降频到FPGA能处理的频段,FPGA进行相应分频输出目标频率,最后通过电平转换电路调节信号的共差模电压实现目标电平输出。选择LVPECL、LVDS和+7 dBm 3种典型电平进行测试,测试结果表明,系统输出频率稳定,误差达到0.025%,转换电平的电压值误差最大为3.268 mV,满足系统设计要求。A multi-interface level output frequency synthesizer is designed to solve the problem that the interface level standards between different chips and devices are different.The signal of 1.6 GHz^3.2 GHz frequency band is generated by the phase-locked loop chip,and the signal generated by the phase-locked loop is down-converted to the frequency band that the FPGA can process by using the parallel-to-serial chip,and the FPGA performs the corresponding frequency-divided output target frequency,and finally passes the level conversion.The common mode voltage of the circuit adjustment signal achieves the target level output.Three typical levels of LVPECL,LVDS and+7 dBm are selected for testing.The test results show that the system output frequency is stable,the error is 0.025%,and the voltage value error of the conversion level is 3.268 mV,which satisfies the system design requirements.

关 键 词：频率综合器 接口电平 锁相环 FPGA 共差模电压 

分 类 号：TN98[电子电信—信息与通信工程]