基于FPGA的相控阵探测器高速信号处理电路  

High Speed Signal Processing Circuit of Phased Array Detector Based on FPGA

作　　者：苑彬[1] 陈书立[2] YUAN Bin;CHEN Shuli(School of Electromechanical Engineering,Henan Polytechnic,Zhengzhou 450046,China;School of Electrical Engineering,Zhengzhou Univercity,Zhengzhou 450001,China)

机构地区：[1]河南职业技术学院机电工程学院,郑州450046 [2]郑州大学电气工程学院,郑州450001

出　　处：《电子器件》2020年第1期128-132,161,共6页Chinese Journal of Electron Devices

基　　金：国家自然科学基金青年基金项目(61603344)。

摘　　要：为了降低相控阵探测器结构的复杂度,基于现场可编程门阵列FPGA设计了五通道高速信号处理电路。采用坐标旋转数字计算机CORDIC和多相分解滤波器设计了数字下变频器,降低每个数据流的处理负担。在波达方向DOA模块中,引入改良的收缩阵列方法,实现了对数据的并行处理,缩短了空间谱的搜索时间。利用嵌入式乘法器和加法器实现了波束形成网络BFN的可编程设计,使响应速度达到了毫秒级。实验结果表明:设计的电路总延迟仅为1.242 ms,能将原始信号放大到近13 dB,方向角测量误差小于1°,实现了对无线电基带信号的高速处理。In order to reduce the complexity of phased array detector structure,a five-channel high speed signal process circuit is designed based on PFPA.The digital down converter is designed using Coordinate Rotating Digital Computer and multiphase decomposition filter,which reduces the processing burden of each data stream.In Direction of Arrival module,an improved shrinkage array method is introduced to realize parallel processing of data and shorten the search time of spatial spectrum.The programmable design of beamforming network is realized by using embedded multipliers and adders,and the response speed reaches millisecond level.The experimental results show that the total delay of the designed circuit is only 1.242 ms,the original signal can be amplified to nearly 13 dB,and the measurement error of direction angle is less than 1 degree,realizing high-speed processing of radio baseband signal.

关 键 词：高速信号处理 相控阵探测器 现场可编程门阵列 特征值分解 多相分解滤波 

分 类 号：TN45[电子电信—微电子学与固体电子学]