基于HEVC的CABAC二进制算术编码器的FPGA实现  

FPGA Implementation of CABAC Binary Arithmetic Encoder Based on HEVC

作　　者：王尧 汤心溢[1,3] WANG Yao;TANG Xinyi(Shanghai Institute of Technical Physics,Key Laboratory of Infrared System Detection and Imaging Technology,Chinese Academy of Sciences,Shanghai 200083,China;University of Chinese Academy of Sciences,Beijing 100049,China;School of Information Science and Technology,Shanghai Tech University,Shanghai 201210,China)

机构地区：[1]中国科学院上海技术物理研究所中国科学院红外探测与成像技术重点实验室,上海200083 [2]中国科学院大学,北京100049 [3]上海科技大学信息科学与技术学院,上海201210

出　　处：《红外技术》2020年第4期335-339,347,共6页Infrared Technology

摘　　要：本文基于H.265/HEVC视频编码标准,实现了CABAC编码中二进制算术编码器常规编码模式下的一种硬件流水线结构,根据算法特性设计并优化了编码器的硬件架构,将概率状态数据储存在SRAM中,并使用查找表优化概率估计更新运算;对编码数据进行打包处理,简化概率估计更新带来的计算,以优化视频数据流编码速度;二进制算术编码采用多级流水线结构,支持四路并行编码。仿真结果表明,本文的硬件CABAC二进制算术编码器平均每时钟周期可以完成4个bin的编码,符合较高帧率的1080p视频实时编码要求。Based on the H.265/HEVC video coding standard,a hardware pipeline structure is implemented in this study in the regular mode of a binary arithmetic encoder in CABAC coding.Based on the characteristics of the algorithm,the hardware architecture of the coding engine is designed and optimized.The probability state data are stored in a SRAM,and the probability estimation updating operation is optimized using a lookup table.The coding data are packaged to simplify the calculation obtained by the update of the probability estimation to optimize the coding speed of the video data stream.Binary arithmetic coding uses a multistage pipeline structure to support four-way parallel encoding.Simulation results show that the hardware of the CABAC binary arithmetic coder can complete the encoding of four bins per clock cycle,which satisfies the higher frame rate of 1080p video real-time encoding requirements.

关 键 词：HEVC 熵编码 CABAC FPGA 二进制算术编码器 

分 类 号：TN919.81[电子电信—通信与信息系统]