基于FPGA多接口的千兆以太网IP核设计  

The Giabit Ethernet IP Core Designing Based on FPGA of Multi-Interface

作　　者：李岚 苏敏 程丽彬 段江霞 LI Lan;SU Min;CHENG Libin;DUAN Jiangxia(Science and Technology on Electronic Information Control Laboratory,Chengdu 610036,China;Unit 95486 of PLA,Chengdu 610000,China;Unit 93808 of PLA,Lanzhou 730000,China)

机构地区：[1]电子信息控制重点实验室,成都610036 [2]解放军95468部队,成都610000 [3]解放军93808部队,兰州730000

出　　处：《电子信息对抗技术》2020年第2期82-88,共7页Electronic Information Warfare Technology

摘　　要：具有嵌入式千兆以太网功能的信号处理类产品,存在GMII,RGMII以及SGMII等模式。采用FPGA作为主控系统,设计了可兼容GMII/RGMII/SGMII模式的UDP网络IP核。该IP核采用用户逻辑搭建的方法在FPGA内部实现了千兆以太网通信功能,且未使用FPGA内嵌CPU,占用FPGA资源较少,具有较强移植性。经过测试验证得出,该IP核传输稳定,可适应多种类型的产品,为数据远程传输及产品调测提供了有效手段。For signal processing product with embedded Gigabit Ethernet capabilities, there are several interface modes of network such as GMII, RGMII,SGMII and so on. The UPD network IP core is designed using FPGA as the main control system, which is compatible with the mode of GMII, RGMII and SGMII. The method of user logic is used by this IP core which can achieve Gigabit Ethernet communication withnot the embedded CPU of FPGA. And less FPGA resources is consumed by this method, and has stronger portability. It is proved that data could be transmitted stably with the IP core, and it is adapted to multiple types of products by testing validation, which could be effective for the remote data transmission and prodcuts debugging.

关 键 词：FPGA 千兆以太网 GMII RGMII SGMII 

分 类 号：TP393.11[自动化与计算机技术—计算机应用技术]