PCI Compiler IP核的外设集成设计与研究  

Design and Research of Peripheral Integration Based on PCI Compiler IP Core

作　　者：赵文龙 Zhao Wenlong(Suzhou Polytechnic Institute of Agricuturre,Suzhou 215008,China)

机构地区：[1]苏州农业职业技术学院,苏州215008

出　　处：《单片机与嵌入式系统应用》2020年第5期58-60,63,共4页Microcontrollers & Embedded Systems

基　　金：2019年苏州市科技发展计划(SNG201918);苏州农业职业技术学院2019年度青年教师提升计划(19NQ1003)。

摘　　要：针对NiosⅡ外设集成无法直接通过PCI接口控制器进行关联和数据交互问题,基于PCI Compiler IP核采用了一种Avalon-to-PCI和PCI-to-Avalon的数据转换方法,实现数据和地址从NiosⅡ处理器Avalon本地总线到外设PCI总线的交互。经验证,在NiosⅡ时钟频率与PCI核时钟一致的情况下,实现PCI外设与NiosⅡ处理器读写交互在最大传输长度为1024字节时数据读写一致,满足NiosⅡ软核基于PCI Compiler IP核外设集成数据传输一致性要求。Aiming at the integration of NiosII peripherals which can not be directly correlated and interacted by PCI interface controller,a data conversion way of Avalon to PCI and PCI to Avalon is adopted based on PCI compiler IP core for realizing the interaction of data and address from Avalon local bus of NiosII processor to PCI main line of peripherals.If the clock frequency of NiosII is consistent with that of PCI core,it has been proved that the data read-write interaction with NiosII processor is consistent when the maximum transmission length is 1024 bytes,meeting the requirements of data transmission consistency of NiosII soft core based on PCI compiler IP core peripheral integration.

关 键 词：接口控制器 本地总线 软核 SOPC 一致性 

分 类 号：TN710.9[电子电信—电路与系统]