基于FPGA的DMA数据传输系统设计  

Design of DMA data transmission system based on FPGA

作　　者：王炳辉 何小海[1] 卿粼波[1] 熊淑华[1] WANG Bing hui;HE Xiao hai;QING Lin bo;XIONG Shu hua(School of Electronics and Information Engineering,Sichuan University,Chengdu 610065,China)

机构地区：[1]四川大学电子信息学院,四川成都610065

出　　处：《电子设计工程》2020年第8期20-24,共5页Electronic Design Engineering

基　　金：国家自然科学基金资助项目(61871279);成都市产业集群协同创新项目(2016-XT00-00015-GX)。

摘　　要：针对数字图像处理过程中的大量数据传输需求,设计了基于FPGA的DMA数据传输系统。上位机基于WinDriver驱动开发工具开发了DMA传输控制程序,下位机基于Xilinx PCIe IP硬核设计了DMA控制逻辑,实现了上位机控制命令发送、数据组包、FPGA端数据读写以及数据乱序重排。经测试该系统DMA写数据速率可达793 MB/s,为理论峰值的79%;DMA读数据速率达752MB/s,为理论峰值的75%,能高效地完成数据传输任务。Aiming at the large amount of data transmission in digital image processing,this paper designs an FPGA-based DMA data transmission system. The host computer developed the DMA transfer control program based on the WinDriver driver development tool. The slave computer designed the DMA control logic based on the Xilinx PCIe IP hard core,which realized the upper computer control command transmission,data group package,FPGA end data read and write,and data disorder. The DMA write data rate of the system is up to 793 MB/s,which is 79% of the theoretical peak value;the DMA read data rate is 752 MB/s,which is 75% of the theoretical peak value,which can efficiently complete the data transmission task.

关 键 词：FPGA DMA 乱序重排 数据传输 

分 类 号：TP39[自动化与计算机技术—计算机应用技术]