基于Verilog HDL的通用UART模块设计与实现  

Design and implementation of verilog HDL-based general purpose UART module

作　　者：吕阳 刘莉娜 郑良广 侯晓伟 LV Yang;LIU Li na;ZHENG Liang guang;HOU Xiao wei(Ningbo CRRC Times Transducer Technology CO.,LTD.,Ningbo 315021,China;Vehicle Bright Engineering Couege,Hunan Automotive Engineering Vocational College,Zhuzhou 412000,China)

机构地区：[1]宁波中车时代传感技术有限公司,浙江宁波315021 [2]湖南汽车工程职业学院车辆工程学院,湖南株洲412000

出　　处：《电子设计工程》2020年第8期174-179,共6页Electronic Design Engineering

基　　金：科技部国家重点研发计划(2016YFB1200401);宁波市工业重大科技专项(2017B10017)。

摘　　要：针对工业控制器等对异步串行通讯应用的广泛需求,基于Verilog HDL语言设计了一种波特率、校验类型、帧长度等参数可灵活配置的UART模块,并采用Modelsim进行了行为级的功能仿真。同时搭建了基于FPGA器件的硬件环境,采用CPLD器件的通讯插件对该UART模块进行了单板测试验证工作。测试结果表明:该UART模块完全能够基于不同结构的PLD器件完成功能设计目标。另外采用该UART模块在国产PLD器件上完成了24小时环回丢包测试,未出现数据错误情况,从而验证了该UART模块功能的有效性及设计的通用性。Asynchronous serial communication is widely used in many fields,including Industrial controller. This paper designs an UART module based on the Verilog HDL language,in which some important parameters can be flexibly configurated,such as baud rate,calibration type,frame length. The function simulation of behavior level is carried out by the Modelsim software. The hardware test environment based on FPGA devices is set up,and single-board test verification of UART module with the communication plug-in based on CPLD devices. The results show that the UART module can completely achieve the design goals based on the different structures of PLD devices. In addition,loop back packet drop test for 24 hours is conducted in UART module with the help of domestic PLD devices,and no data error conditions appear. The results further verify the effectiveness of the UART module function and design versatility.

关 键 词：HDL UART 波特率 校验类型 帧长度 

分 类 号：TP23[自动化与计算机技术—检测技术与自动化装置]