基于FPGA的万兆以太网TCP/IP协议处理架构  

10 Gigabit Ethernet TCP/IP protocol stack processing architecture based on FPGA

作　　者：吴惑 刘一清[1] WU Huo;LIU Yi qing(School of Information Science and Technology,East China Normal University,Shanghai 200241,China)

机构地区：[1]华东师范大学通信与电子工程学院,上海200241

出　　处：《电子设计工程》2020年第9期81-87,共7页Electronic Design Engineering

摘　　要：针对如今万兆网络流量服务器处理的瓶颈问题,提出了一种基于FPGA的万兆以太网TCP/IP协议处理架构。通过在处理架构中划分控制平面和数据平面,使各个逻辑电路模块的协同操作,并结合高速的I/O处理和存储器处理,利用硬件实现了完整的TCP/IP协议栈,有效的解决了服务器处理万兆网络流量的瓶颈问题。将所提出的架构应用于实际万兆以太网TCP/IP卸载板卡中,其协议支持ARP、ICMP、UDP、TCP等,并且时延最低可达0.288μs,文件传输速率可达933 MB/s,CPU资源占用率仅为10%,光口有效数据吞吐率可达9.034 Gbps。In view of the problem of today's 10G network traffic by processing server,this paper proposes an FPGA based 10 Gigabit Ethernet TCP/IP protocol processing architecture.By dividing the control plane and data plane in the processing architecture,the cooperative operation of each logic circuit module,combined with high speed I/O processing and memory processing,the complete TCP/IP protocol stack is realized by hardware,which effectively solves the bottleneck of 10 Gigabit network traffic by server processing.This proposed architecture is the actual 10 Gigabit Ethernet TCP/IP offload board,which supports the protocol of ARP,ICMP,UDP,TCP,etc.The delay is as low as 0.288us,and the file transfer rate is up to 933MB/s with 10%CPU resource usage.The effective data throughput rate of the optical port can reach 9.034Gbps.

关 键 词：万兆以太网 FPGA TCP/IP协议栈 TOE 

分 类 号：TN393.1[电子电信—物理电子学]