基于互连线电容耦合的SR锁存电路研究  

Research on SR latch circuit based on interconnected coupling capacitor

作　　者：赵志伟 张跃军[1,2] 李林 ZHAO Zhiwei;ZHANG Yuejun;LI Lin(Faculty of Electrical Engineering and Computer Science,Ningbo University,Ningbo 315211,China;State Key Laboratory of Cryptology,Beijing 100878,China)

机构地区：[1]宁波大学信息科学与工程学院,浙江宁波315211 [2]密码科学技术国家重点实验室,北京100878

出　　处：《宁波大学学报（理工版）》2020年第3期50-56,共7页Journal of Ningbo University：Natural Science and Engineering Edition

基　　金：国家自然科学基金(61871244,61874078);浙江省自然科学基金(LY18F040002);国家重点实验室开放课题(MMKFKT20187);专用集成电路与系统国家重点实验室开放研究课题(2019KF002);宁波大学研究生科研创新项目.

摘　　要：通过对线间电容耦合模型的研究,提出了一种基于互连线电容耦合的SR锁存电路设计方案.该方案首先分析互连线间电容耦合关系,利用MOS管栅极电容模拟互连线电容;然后利用电容耦合结构与线计算特性,设计或非逻辑门电路,在此基础上实现基于互连线电容耦合的SR锁存电路;最后在TSMC65 nmSpectre环境下仿真验证.结果表明:所设计的电路逻辑功能正确,且具有低硬件开销特性.With the on-going improvement of integrated circuit technology,there are more and more resources with the on-chip interconnection.By studying the capacitive coupling model between lines,in this paper a design scheme of SR latch circuit is proposed based on interconnected capacitance coupling.Capacitance coupling relationship between interconnected lines is established using MOS gate capacitance to simulate interconnected capacitance,and then using capacitive coupling structure and line calculation characteristics.Through designing or NOR gate,SR is implemented based on interconnected capacitance coupling latch circuit.Finally,the simulation is conducted to verify the proposed design in the TSMC 65 nm Spectre environment.The results show that the designed circuit logic function is valid and has low hardware overheads.

关 键 词：或非门 SR锁存电路 线电容耦合 电路设计 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]