高速串行总线RapidlO与PCI Express动态可重配置设计  

RapidIO and PCI express partial reconfiguration design based on high-speed serial transceiver

作　　者：张月皓 柳桃荣 余开 郭柳柳 Zhang Yuehao;Liu Taorong;Yu Kai;Guo Liuliu(Brainware Terahertz Information Technology Co.,Ltd,Hefei 231500,China)

机构地区：[1]博微太赫兹信息科技有限公司,合肥230000

出　　处：《电子测量技术》2020年第3期86-91,共6页Electronic Measurement Technology

摘　　要：通过分析当前串行RapidIO协议与PCI Express协议,利用RapidIO与PCI Express在物理层的共同特性,针对多种高速串行接口协议SoC系统设计需求,提出了一种共PHY的高速SoC设计。通过FPGA的动态重配置功能,使用FPGA串行高速收发器GTX,动态转发RapidIO和PCI Express协议包。利用FPGA上的重配置分割,将控制器上层多路选择器放入可重配置部分,实现DMA到多路选择器的可重配设计。实验测试使用两片Virtex-72000T FPGA芯片互联,传输的峰值吞吐量可以达到9.5 Gbps,资源利用率降低到原来的72.8%,系统的灵活性大幅提高。Through analyzing RapidIO and PCI Express protocol,using the common features of RapidIO and PCI Express Physical layer,to meet requirements of SoC system design for various high speed serial interface,one SoC design with the common PHY is proposed.based on FPGA High-speed Serial Transceiver and Partial Reconfiguration,The system can route RapidIO packets or PCI Express packets dynamically by User Logic.With consideration of Reconfiguration Partition based on FPGA,reconfigure the multiplexer of controller and DMA transfer.There are two Virtex-72000 T FPGA connected in this system,the peak throughput of this system can be 9.5 Gbps,the performance can be improved and resource utilization decreased to 72.8%of the original design.

关 键 词：RAPIDIO协议 PCI Express协议 动态重配置 

分 类 号：TP336[自动化与计算机技术—计算机系统结构]