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作 者:陈建国 方振国[1] 柏雪婷 CHEN Jian-guo;FANG Zhen-guo;BAI Xue-ting(School of Physics and Electronic Information ,Huaibei Normal University, Huaibei Anhui 235000,China;Shanghai Qisheng Electric Co., Ltd., Shanghai 200000,China)
机构地区:[1]淮北师范大学物理与电子信息学院,安徽淮北235000 [2]上海旗升电气有限公司,上海200000
出 处:《佳木斯大学学报(自然科学版)》2020年第2期48-51,共4页Journal of Jiamusi University:Natural Science Edition
基 金:省级质量工程项目(2018jyssf036,2016zy109,2017jyxm0210);校级教学研究项目(2017jyxm07)。
摘 要:针对组合电路的智能化设计速度慢、复杂度高的问题,利用基于人工智能的自主搜索优化策略,将树搜索优化算法与组合逻辑电路中相邻最小项合并定理融合,并在可编程门阵列(Field Programmable Gate Array,FPGA)进行硬件加速的方法进行组合电路的智能设计。该方法把需要设计的逻辑电路最小项作为一级节点,搜索本级中可以合并消项的节点并把合并后的项作为子节点,逐级向下搜索直到本级节点均不能合并消项,最后把所有叶子节点项相加即得到组合逻辑电路的最简逻辑表达式,从而完成组合逻辑电路的智能设计过程。算法通过使用启发式策略,简化了搜索过程,提高了搜索速度。实验结果证明了与传统算法作比较,该算法具有空间复杂度低,速度快等特点。Using the strategy of independent search and optimization based on artificial intelligence,the problem of low speed and high complexity in the intelligent design of combinational circuit is solved.The tree search optimization algorithm is combined with the merging theorem of the adjacent minimum term in the combinational logic circuit,and the intelligent design of the combinational circuit is carried out by the method of hardware acceleration in the field programmable gate array(FPGA).This method takes the minimum term of the logic circuit to be designed as the first level node,searches the nodes in the current level that can merge the cancellation terms and takes the merged items as the sub nodes,and searches down level by level until the nodes in the current level cannot merge the cancellation terms.Finally,the simplest logic expression of combinational logic circuit is obtained by adding all leaf nodes.By using heuristic strategy,the algorithm simplifies the search process and improves the search speed.The experimental results show that compared with the traditional algorithm,the algorithm has the characteristics of low space complexity and high speed.
分 类 号:TN402[电子电信—微电子学与固体电子学]
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