Design Optimization of Pillar Bump Structure for Minimizing the Stress in Brittle Low K Dielectric Material Layer  

作　　者：Xin-Jiang Long Jin-Tang Shang Li Zhang 

机构地区：[1]Key Laboratory of MEMS of Ministry of Education,Southeast University,Sipailou 2#,Nanjing 210096,China [2]Jiangyin Changdian Advanced Packaging Co.,Ltd.,No.275 Binjiang Rd,Jiangyin 214400,China

出　　处：《Acta Metallurgica Sinica(English Letters)》2020年第4期583-594,共12页金属学报（英文版）

基　　金：The technical support and discussion from Cheng Xu,Kim-Hwee Tan and Zhi-Quan Liu are acknowledged.

摘　　要：Cu pillar bump offers a number of advantages for flip chip packaging,compared to the conventional solder bump.However,due to its rigidity structure,Cu pillar bump introduces a lot of stress to the chip,which causes the failure of packaging structures,especially for the advanced node devices which typically have brittle low K dielectric material.In this paper,for the first time we propose two types of Cu pillar structures to reduce the stress.The first Cu pillar structure has bigger Cu dimensions at the base.The other one is designed to add an additional Cu pad under the Cu pillar bump.Finite element analysis is used to study the stress of the both structures,and it is found that with the increase in pillar bump contact area over the chip surface,the stress decreases in both structures.Results also indicate that the Cu pillar bump undercut induces higher stress,and thin Cu6 Snss intermetallic compound has less impact on the stress during flip chip mount reflow.The study provides a novel way to improve the reliability by reducing the stress in the Cu pillar bump related packaging.

关 键 词：Cu PILLAR BUMP FLIP chip Low K STRESS UNDERCUT 

分 类 号：TN405[电子电信—微电子学与固体电子学]