基于FPGA的量子通信中经典信道的设计与实现  

Design and implementation of FPGA-based classical channel for quantum communication

作　　者：邓雄峰 刘震宇[1] 郑玉鳞 贺佳坤 DENG Xiongfeng;LIU Zhenyu;ZHENG Yulin;HE Jiakun(School of Information Engineering,Guangdong University of Technology,Guangzhou 510000,China;Hisilicon Research Department,Huawei Technologies Co.,Ltd.,Shenzhen 518129,China)

机构地区：[1]广东工业大学信息工程学院,广东广州510000 [2]华为技术有限公司海思研究部,广东深圳518129

出　　处：《现代电子技术》2020年第9期33-36,40,共5页Modern Electronics Technique

基　　金：广州市产学研协同创新重大专项(201704030093)。

摘　　要：为满足量子密钥分发中对经典信道的设计需求,设计了一种片上可编程系统+FPGA+PHY芯片的经典信道解决方案。在FPGA内部构建片上可编程系统,通过NiosⅡ运行NicheStack TCP/IP实现TCP通信协议,并使用三速以太网IP和物理层芯片Marvel 88E1111实现以太网控制器。指令处理器软件结构易于将基于FPGA的经典以太网信道与量子态信号处理算法相结合实现,对量子通信系统小型化和集成化都具有重要意义。该方案在StratixⅣ上进行了实现。测试结果表明,系统端数据接口速度可达1600 Mb/s,经典信道上行数据传输速度最高可达61 Mb/s,相较已有同类型设计提高了约20%的性能。In order to satisfy the design requirements of the classical channel layer in a quantum key distribution system,a classical communication solution for the chip with system-on-programmable-chip+FPGA+PHY is designed.A system-on-programmable-chip is established inside the FPGA.The system runs the NicheStack TCP/IP by Nios II to realize TCP,and employs a three-speed Ethernet IP and a physical layer chip Marvel 88E1111 to implement the Ethernet controller.An instruction-processor software architecture is proposed,which is optimized to run both classical Ethernet communications and quantum state signal processing algorithms within the same FPGA.This feature is critical to the miniaturization and integration of quantum communication systems.This solution is implemented on Stratix IV.The test results show that the data interface speed of the system terminal can reach up to 1600 Mb/s,and the classical channel′s uplink data speed can reach a data transmission rate of up to 61 Mb/s,which is increased by 20%of the performance in comparison with the existing design of the same type.

关 键 词：经典信道 量子通信 量子密钥分发 编译器优化 系统集成 以太网控制器 

分 类 号：TN911.22-34[电子电信—通信与信息系统] TP393.1[电子电信—信息与通信工程]