Parallelization of motion compensation algorithm based on reconfigurable video array processor  

作　　者：Xie Xiaoyan Lei Xiang Zhou Jinna Zhu Yun Jiang Lin 

机构地区：[1]School of Computer,Xi'an University of Posts and Telecommunications,Xi'an 710121,China [2]School of Electronic Engineering,Xi'an University of Posts and Telecommunications,Xi'an 710121,China [3]Integrated Circuit Design Laboratory,Xi'an University of Science and Technology,Xi'an 710054,China

出　　处：《The Journal of China Universities of Posts and Telecommunications》2019年第6期83-93,共11页中国邮电高校学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(61834005,61772417,61802304,61874087,61602377,61634004,61272120);the Shaanxi Province Coordination Innovation Project of Science and Technology(2016KTZDGY02-04-02);the Shaanxi Provincial Key R&D Plan(2017GY-060);Shaanxi International Science and Technology Cooperation Program(2018KW-006)。

摘　　要：The new encoding tools of high efficiency video coding(HEVC) make the interpolation operation more complex in motion compensation(MC) for better video compression, but impose higher requirements on the computational efficiency and control logic of the hardware architecture. The reconfigurable array processor can take into consideration both the computational efficiency and flexible switching of algorithms very well. Through mining the data dependency and parallelism among interpolation operation, this paper presents a parallelization method based on the dynamic reconfigurable array processor proposed by the project team. The number of pixels loaded from the external memory is reduced significantly, by multiplexing the common data in the previous reference block and the current reference block. Flexible switching of variable block operation is realized by using dynamic reconfiguration mechanism. A 16×16 processor element(PE)’s array is used to dynamically process a 4×4-64×64 block size. The experimental results show that, the reference block update speed is increased by 39.9%. In the case of an array size of 16 PEs, the number of pixels processed in parallel reaches 16.The new encoding tools of high efficiency video coding(HEVC) make the interpolation operation more complex in motion compensation(MC) for better video compression, but impose higher requirements on the computational efficiency and control logic of the hardware architecture. The reconfigurable array processor can take into consideration both the computational efficiency and flexible switching of algorithms very well. Through mining the data dependency and parallelism among interpolation operation, this paper presents a parallelization method based on the dynamic reconfigurable array processor proposed by the project team. The number of pixels loaded from the external memory is reduced significantly, by multiplexing the common data in the previous reference block and the current reference block. Flexible switching of variable block operation is realized by using dynamic reconfiguration mechanism. A 16×16 processor element(PE)’s array is used to dynamically process a 4×4-64×64 block size. The experimental results show that, the reference block update speed is increased by 39.9%. In the case of an array size of 16 PEs, the number of pixels processed in parallel reaches 16.

关 键 词：HEVC MC PARALLELIZATION RECONFIGURABLE 

分 类 号：TN919.81[电子电信—通信与信息系统] TP332[电子电信—信息与通信工程]