一种适用于严重衰减串行链路的3.3 Gbit/s模拟均衡器  

A 3.3 Gbit/s Analog Equalizer for Severely Lossy Serial link

作　　者：袁小方 段吉海[1] 张秀峰[1] 韦雪明[1] 徐卫林[1] YUAN Xiaofang;DUAN Jihai;ZHANG Xiufeng;WEI Xueming;XU Weilin(Guangxi Key Laboratory of Precision Navigation Technology and Application,Guilin University of Electronic Technology,Guilin Guangxi 541004,China)

机构地区：[1]桂林电子科技大学广西精密导航技术与应用重点实验室,广西桂林541004

出　　处：《电子器件》2020年第2期349-353,共5页Chinese Journal of Electron Devices

基　　金：国家自然科学基金项目(61161003);广西自然科学基金项目(201755A170452y);广西精密导航技术与应用重点实验室主任基金项目(DH201806)。

摘　　要：介绍了一种用于严重损耗串行链路的连续时间线性均衡器(CTLE)。为了解决传统均衡器存在的过均衡和欠均衡问题,提出了一种低频增益线性可调的改进结构,实现了对不同衰减信道的增益补偿。该结构主要包括均衡滤波模块和直流失调消除模块。均衡滤波模块采用均衡单元串联的结构,提高了对信号高频成分的补偿能力。直流失调消除模块用来消除芯片制造过程中因失配而产生的直流偏移。电路采用TSMC 0.18μm CMOS工艺设计,总面积为1.2 mm×0.65 mm。测试结果表明,当速率为3.3 Gbit/s的数据通过损耗为18.8 dB的信道时,均衡器工作正常。在1.8 V的供电电压下,芯片整体功耗为124.2 mW。A continuous-time linear equalizer(CTLE)for severely lossy serial links is introduced. In order to solve the problems of over-equalization and under-equalization in traditional equalizers,an improved structure with linear adjustable low-frequency gain is proposed,which can compensate the gain of different attenuation channels. The structure mainly includes equalization filter module and DC offset elimination module. The equalization filter module adopts the structure of equalization units in series,which improves the compensation ability of high frequency components of signals. DC offset elimination module is used to eliminate DC offset caused by mismatch in chip manufacturing process. The circuit is fabricated in TSMC 0.18-μm CMOS process and its overall area is 1.2 mm×0.65 mm. The measurement results show that the equalizer works normally when equalizing 3.3 Gbit/s data passes through the channel with a loss of 18.8 dB. The power consumption of the equalizer is 124.2 mW for the supply voltage of 1.8 V.

关 键 词：均衡器 严重损耗的串行链路 串行结构 直流失调消除环路 

分 类 号：TN43[电子电信—微电子学与固体电子学]