基于CRC与比特交织的LDPC码3D Flash差错控制方法研究  

3D Flash Error Control Method Based on CRC and Bit Interleaving LDPC Code

作　　者：郏宏鑫 郭锐[1] JIA Hong-xin;GUO Rui(College of Communication Engineering,Hangzhou Dianzi University,Hangzhou 310018,China)

机构地区：[1]杭州电子科技大学通信工程学院,浙江杭州310018

出　　处：《软件导刊》2020年第4期247-251,共5页Software Guide

基　　金：浙江省自然科学基金项目(LY16F010013);浙江省重点科技创新团队基金项目(2013TD03)。

摘　　要：为解决3D Flash存储密度增大导致Flash整体误码率不断提高、数据可靠存储时间缩短的问题,提出一种基于循环冗余校验与比特交织的LDPC码3D Flash差错控制方法。该方法首先用CRC判决读取数据是否出错,若出错则实施LDPC纠错,避免浪费纠错资源。在数据读写过程中使用比特交织的方法改变3D TLC Flash逻辑页的比特信息存放顺序,降低3D Flash单一逻辑页误码率过高引起的不必要坏区发生概率。仿真结果表明,在3D TLC Flash信道下,LSB逻辑页的比特误码率下降约35.7%,Flash数据保留时间增加了30.9%。该差错控制方法可在3D TLC Flash控制器中实现,不仅可提高3D TLC Flash数据存储可靠性,还可延长3D TLC Flash数据可靠存储时间。In order to improve the overall bit error rate(BER)and reliable data storage time of 3D Flash with the increase of storage density.In this paper,a 3D Flash error control method based on cyclic redundancy check and bit interleaving LDPC code is proposed.This method first uses CRC to judge whether the data is erroneous.After the error,the LDPC error correction step is performed,which reduces unnecessary error correction performance is wasted.In the process of data reading and writing,the method of bit interleaving is used to change the order of storing bit information in the 3D TLC Flash logical page,which reduces the unnecessary bad area caused by the high bit error rate of single logical page in 3D Flash.The simulation results show that In the 3D TLC Flash channel environment,the bit error rate of the LSB logical page decreases by approximately 35.7%,and the Flash data retention time increases by 30.9%.The error control method improves the reliability of 3D TLC Flash data storage and prolongs the reliable storage time of 3D TLC Flash data,which can be implemented in the 3D TLC Flash controller.

关 键 词：三维三层单元闪存 低密度奇偶检验码 循环冗余校验 比特交织 差错控制 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]