一种新型分段延时型DPWM的设计与实现  

Design and implementation of a new segmented delay DPWM

作　　者：程心[1] 许立新 陈亮 张章[1] CHENG Xin;XU Lixin;CHEN Liang;ZHANG Zhang(School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230601, China;Anhui Academy of Science and Technology, Hefei 230001, China)

机构地区：[1]合肥工业大学电子科学与应用物理学院,安徽合肥230601 [2]安徽省科学技术研究院,安徽合肥230001

出　　处：《合肥工业大学学报（自然科学版）》2020年第5期640-645,共6页Journal of Hefei University of Technology：Natural Science

基　　金：国家自然科学基金资助项目(61674049);中央高校基本科研业务费专项资金资助项目(PA2018GDQT0017)。

摘　　要：文章提出一种基于现场可编程门阵列(field programmable gate array,FPGA)的分段延时型数字脉宽调制模块(digital pulse width modulator,DPWM),将二进制的输入信号分成3段,分别分配给计数器、相移电路和快速进位链,以产生精度不同的3段延时叠加,从而形成高时间分辨率的脉宽调制(pulse width modulator,PWM)信号;分析了在相移电路中潜在的时序与逻辑错误,设计新型的相移电路解决上述问题。此外,利用加法器进位延时综合成为快速进位链,在提高时间分辨率的同时减少所占用的资源。通过Altera Cyclone IV系列FPGA板测试表明,在14 bit位宽、156 MHz工作频率下,该文设计的DPWM时间分辨率达到50 ps,线性度大于99.2%。This paper proposes a field programmable gate array(FPGA)-based segmented delay digital pulse width modulator(DPWM),which divides the binary input signal into three parts.The divided data are assigned to a counter,a phase shift circuit,and a fast carry chain respectively.These modules produce three delays with different precision and then superimpose these delays to form a high time resolution pulse width modulator(PWM)signal.The potential timing and logic errors in the phase shift circuit are analyzed,and a new phase shift circuit is designed to solve these problems.Furthermore,this paper improves the time resolution of the fast carry chain while reducing its occupied resources.The whole design is verified in Altera Cyclone IV series FPGA.Experimental results show that the proposed DPWM achieves a time resolution of 50 ps and a linearity greater than 99.2%,in the case of 14 bit and 156 MHz frequency.

关 键 词：数字脉宽调制模块(DPWM) 时间分辨率 相移电路 快速进位链 线性度 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]