可重构的SHA-3算法流水线结构优化及实现  

Reconfigurable SHA-3 Pipeline Structure Optimization and Implementation

作　　者：周雍浩 董婉莹 李斌[2] 陈晓杰 冯峰 ZHOU Yong-hao;DONG Wan-ying;LI Bin;CHEN Xiao-jie;FENG Feng(School of Electrical Engineering,Zhengzhou University,Zhengzhou 450001;School of Information Engineering,Zhengzhou University,Zhengzhou 450001;State Key Laboratory of Mathematical Engineering and Advanced Computing,The PLA Information Engineering University,Zhengzhou 450001)

机构地区：[1]郑州大学电气工程学院,郑州450001 [2]郑州大学信息工程学院,郑州450001 [3]中国人民解放军信息工程大学数学工程与先进计算国家重点实验室,郑州450001

出　　处：《现代计算机》2020年第12期15-20,共6页Modern Computer

基　　金：国家重点研发计划基金资助项目(No.2016YFB0800100)。

摘　　要：SHA3算法在网络安全方面具有十分重要的意义和广泛的应用,在现代加密学中占据很重要的地位。为了提高SHA3算法的时钟频率和吞吐量,使其效率最大化,提出可重构的SHA3算法流水线结构及其优化、实现。结合FP⁃GA高效能的优势,对SHA3算法深入分析,缩短关键路径,使用全流水线结构及展开的方式进行优化改进,有效地提高工作频率和计算速度。实验结果表明,该方法最高频率可达415MHz,最高计算速度为3200M次/秒,且能效比相比于GPU提高5.65倍。The SHA3 algorithm has very important significance and extensive applications in network security,and occupies a very important position in modern encryption.In order to improve the clock frequency and throughput of the SHA3 algorithm and maximize its efficiency,In this paper,we present a reconfigurable SHA3 algorithm pipeline structure and its optimization and implementation.Combining the advantages of FPGA's high performance,in-depth analysis of the SHA3 algorithm,shortening the critical path,using a full-pipeline structure and ex⁃pansion methods to optimize and improve,effectively improve the operating frequency and calculation speed.Experimental results show that the maximum frequency of this method is 415 MHz,the maximum calculation speed is 3200 M/s,and the energy efficiency ratio is 5.65 times higher than that of GPU.

关 键 词：SHA-3 FPGA 流水线技术 高效能 密码算法 

分 类 号：TP301.6[自动化与计算机技术—计算机系统结构]