一种16bit2.5GS/s高动态性能数模转换器设计  

Design of a 16 bit 2.5 GS/s High Dynamic Performance Digital-to-Analog Converter

作　　者：张理振[1] 吴俊杰[1] 刘海涛[1] 沈逸骅 Zhang Lizhen;Wu Junjie;Liu Haitao;Shen Yihua(Nanjing Research Institute of Electronics Technology,Nanjing 210039,China)

机构地区：[1]南京电子技术研究所,南京210039

出　　处：《半导体技术》2020年第5期338-344,共7页Semiconductor Technology

摘　　要：设计了一种高动态性能电流舵数模转换器(DAC),其满摆幅输出电流为20 mA。采用三段分段结合低位R-2R网络的混合分段结构,整个DAC仅使用了两种不同尺寸的电流源单元。采用模拟前台校准技术对这两种电流源及其比例关系进行校准,以较小的尺寸实现较高的匹配性,同时引入共源共栅MOSFET和抽血电流源进一步提高了输出阻抗,降低了差分端输出阻抗差异,最终提高了DAC的动态性能。采用TSMC 55 nm CMOS工艺进行了流片验证。测试结果表明,2.5 GS/s采样速率下、输出信号频率1.000 9 GHz时,该DAC的无杂散动态范围为62.21 dBc,噪声功率谱密度约为-154 dBm/Hz,功耗约为226 mW,芯片面积为2.5 mm×1.8 mm。A high dynamic performance current-steering digital-to-analog converter(DAC) with a full-scale output current of 20 mA was designed. A three-section hybrid segmented architecture with the R-2 R output network in low segment bits was adopted, and only two current source units of different sizes were used for the whole DAC. The analog foreground calibration technology was adopted to calibrate these two current sources and their proportional relationship to reduce mismatch error with a small size. Meanwhile, the cascode MOSFET and bleed current source were added to increase the output impedance, decrease the output impedance difference in the differential terminal, and finally improve the dynamic performance of the DAC. The DAC was fabricated and verified in TSMC 55 nm CMOS process. The test results show that the DAC has a spurious free dynamic range of 62.21 dBc, a noise power spectral density of about-154 dBm/Hz, a power consumption of about 226 mW at 2.5 GS/s sampling rate and 1.000 9 GHz output signal frequency. The chip area is 2.5 mm×1.8 mm.

关 键 词：数模转换器(DAC) 电流舵 抽血电流源 前台校准 动态性能 

分 类 号：TN432[电子电信—微电子学与固体电子学]