A 0.1–1.5 GHz multi-octave quadruple-stacked CMOS power amplifier  

作　　者：Shizhe Wei Haifeng Wu Qian Lin Mingzhe Zhang 

机构地区：[1]School of Microelectronics,Tianjin University,Tianjin 300072,China [2]Chengdu Ganide Technology,Chengdu 610073,China [3]College of Physics and Electronic Information Engineer,Qinghai University for Nationalities,Xining 810007,China

出　　处：《Journal of Semiconductors》2020年第6期44-47,共4页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(No.61841110);AoShan Talents Outstanding Scientist Program by Pilot National Laboratory for Marine Science and Technology(Qingdao)(No.2017ASTCP-OS03)。

摘　　要：In this letter,we design and analyze 0.1–1.5 GHz multi-octave quadruple-stacked CMOS power amplifier(PA)in 0.18μm CMOS technology.By using two-stage quadruple-stacked topology and feedback technology,the proposed PA realizes an ultra-wideband CMOS PA in a small chip area.Wideband impedance matching is achieved with smaller chip dimension.The effects of feedback resistors on the RF performance are also discussed for this stacked-FET PA.The PA shows measured input return loss(<–10.8 dB)and output return loss(<–9.6 dB)in the entire bandwidth.A saturated output power of 22 dBm with maximum 20%power added efficiency(PAE)is also measured with the drain voltage at 5 V.The chip size is 0.44 mm^2 including all pads.

关 键 词：power amplifier CMOS stacked multi-octave resistive matching 

分 类 号：TN722.75[电子电信—电路与系统]