An 18-bit sigma–delta switched-capacitor modulator using 4-order single-loop CIFB architecture  

作　　者：Guiping Cao Ning Dong 

机构地区：[1]Research Center of High Speed Machine Vision of Hefei,Hefei 230088,China

出　　处：《Journal of Semiconductors》2020年第6期62-70,共9页半导体学报（英文版）

基　　金：funded by the Major Emerging Industrial Projects of Anhui;the Postdoctoral Project from Hefei

摘　　要：Oversampling sigma–delta(Σ–Δ)analog-to-digital converters(ADCs)are currently one of the most widely used architectures for high-resolution ADCs.The rapid development of integrated circuit manufacturing processes has allowed the realization of a high resolution in exchange for speed.Structurally,theΣ–ΔADC is divided into two parts:a front-end analog modulator and a back-end digital filter.The performance of the front-end analog modulator has a marked influence on the entireΣ–ΔADC system.In this paper,a 4-order single-loop switched-capacitor modulator with a CIFB(cascade-of-integrators feed-back)structure is proposed.Based on the chosen modulator architecture,the ASIC circuit is implemented using a chartered 0.35μm CMOS process with a chip area of 1.72×0.75 mm^2.The chip operates with a 3.3-V power supply and a power dissipation of 22 mW.According to the results,the performance of the designed modulator has been improved compared with a mature industrial chip and the effective number of bits(ENOB)was almost 18-bit.

关 键 词：sigma–delta modulator OVERSAMPLING CIFB structure SWITCHED-CAPACITOR 

分 类 号：TN792[电子电信—电路与系统] TM53[电气工程—电器]