超低延迟的数据中心网络控制平面设计  

Design of Ultra-Low Delay Control Plane for Data Center Network

作　　者：荆倩 沈三民[1] JING Qian;SHEN Sanmin(Key Laboratory of Instrument Science and Dynamic Testing, Ministry of Education, Zhongbei University, Taiyuan 030051, China)

机构地区：[1]中北大学仪器科学与动态测试教育部重点实验室,太原030051

出　　处：《兵器装备工程学报》2020年第5期134-138,共5页Journal of Ordnance Equipment Engineering

基　　金：国家自然科学基金项目(61335008)。

摘　　要：为了降低数据中心网络的延迟和功耗,设计了一种超低延迟的控制平面,包括2个FPGA板,由分立光学元件组成的一个2×2纵横式光交换机。通过高速调度和在并行波分复用信道上的预测性分组传输,实现了纳秒级的分组交换。为了缩短关键路径,提出了一种两阶段分配电路设计,将仲裁和新授权的生成分为两个流水线阶段;以并行的方式分别执行新的服务器请求和来自交换机的缓冲器请求。所提设计在32×32的纵横式光交换机上进行实验,结果表明,在全容量下保持低于10μs的平均端到端延迟,实现55.2 ns的最小端到端延迟。Aiming at reducing the delay and power consumption of a data center network,a control plane with ultra-low delay was designed.It consists of two FPGA boards and a 2×2 vertical and horizontal optical switch composed of discrete optical elements.Through high-speed scheduling and predictive packet transmission over parallel wavelength division multiplexing channels,nanosecond packet switching was realized.To shorten the critical path,a two-stage allocation circuit design was proposed,which divides the arbitration and new authorization components into two pipeline stages,and executes the new server requests and buffer requests from switches in parallel.The proposed design was tested on a 32×32 vertical and horizontal optical switch.The results show that the average end-to-end delay of fewer than 10 microseconds can be maintained at full capacity and the minimum end-to-end delay of 55.2 ns can be achieved.

关 键 词：数据中心网络 控制平面 端到端延迟 波分复用 两阶段分配电路 

分 类 号：TP391[自动化与计算机技术—计算机应用技术] TN929[自动化与计算机技术—计算机科学与技术]