Systolic B-1 Circuit in Galois Fields Based on a Quaternary Logic Technique  

作　　者：Haixia Wu Yilong Bai Tian Wang Xiaoran Li Long He 

机构地区：[1]School of Information and Electronics,Beijing Institute of Technology,Beijing 100081,China

出　　处：《Journal of Beijing Institute of Technology》2020年第2期177-183,共7页北京理工大学学报（英文版）

基　　金：Supported by the National Natural Science Foundation of China(61801027)。

摘　　要：In order to improve the circuit complexity and reduce the long latency of B-1 operations,a novel B-1 operation in Galois Field GF(24)is presented and the corresponding systolic realization based on multiple-valued logic(MVL)is proposed.The systolic structure employs multiplevalued current mode(MVCM)by using dynamic source-coupled logic(SCL)to reduce the initial delay and the transistor and wire counts.The performance is evaluated by HSPICE simulation in 0.18μm CMOS technology and a comparison is conducted between our proposed implementation and those reported in the literature.The initial delay and the sum of transistors and wires in our MVL design are about 43%and 13%lower,respectively,in comparison with other corresponding binary CMOS implementations.The systolic architecture proposed is simple,regular,and modular,well suited for very large scale integration(VLSI)implementations.The combination of MVCM circuits and relevant algorithms based on MVL seems to be a potential solution for high performance arithmetic operations in GF(2k).

关 键 词：multiple-valued logic(MVL) systolic B^-1 circuit Galois Fields 

分 类 号：TN543[电子电信]