Sigma Delta ADC中高抽取率滤波器设计  

Decimation filter design for high-order Sigma Delta ADCs

作　　者：郑伟 高博[1] 刘玥伽 林志滨 龚敏[1] Zheng Wei;Gao Bo;Liu Yuejia;Lin Zhibin;Gong Min(College of Physics,Sichuan Univ.,Chengdu 610065,China)

机构地区：[1]四川大学物理学院,成都610065

出　　处：《电子测量技术》2020年第6期160-164,共5页Electronic Measurement Technology

摘　　要：为了解决高阶Sigma-Delta模数转换器(ADC)在折叠带附近噪声衰减不足的问题,针对积分梳状(CIC)函数的零点进行分析,采用了一种零点偏移sinc函数(RS)提高了折叠带附近噪声抑制能力。针对设计中高抽取率和低功耗要求,采用RS函数作为Sigma Delta抽取滤波器的第一级,其后级联两级FIR滤波器完成一款抽取率为256的数字抽取器。5阶RS滤波器,降低了折叠带附近的高频噪声折叠到基带的的影响;第二级和第三级采用转置结构FIR滤波器分别进行32和2的抽取,转置结构的FIR滤波器能够实现了高吞吐量数据处理。整体结构基于0.18μm CMOS标准工艺,结合4阶级联结构、4 bit量化sigma delta调制器结构,可以在20 MHz工作频率下获得160 dB以上的动态范围,最终输出数据有效位数(ENOB)达24 bit,功率为15 MW,面积3.9 mm^2。In order to solve the problem of insufficient noise attenuation near the folding band of high-order Sigma-Delta analog-to-digital converters(ADC),zero-point analysis is applied to Cascade Integrator Comb(CIC)function in this paper,and a method to offset the zero point of the traditional CIC function is proposed to obtain a much better noise suppression near the folding band.According to the requirements of high decimation filter and low power consumption,the RS function is implemented in hardware as the first stage of the Sigma Delta decimation filter,and then two stages of FIR filters are cascaded to form a digital decimation filter with a decimation rate of 256.The 5 th-order RS filter implements a decimation factor of 4.Compared with conventional CIC filter,the influence caused by the high-frequency noise near the folding band folded into the baseband is reduced.The second and third stages use the transposed FIR filter to perform 32 and 2 decimation,respectively,and the transposed structure of the FIR filter can achieve high throughput during data processing.The decimation filter is designed based on 0.18μm CMOS process.Along with a modulator with 4-stage cascade structure and 4 bit quantization,under a sampling rate of 20 MHz,the decimation filter can reach a dynamic range(DR)of 160 dB and an efficient number of bits(ENOB)of 24 bits,with a power consumption of 15 MW and an area of 3.9 mm^2.

关 键 词：SIGMA-DELTA模数转换器 5阶RS滤波器 高精度 数字抽取器 FPGA 

分 类 号：TN4[电子电信—微电子学与固体电子学]