一种应用于星载交换机的DDR3共享存储交换结构的设计与实现  

Design and Implementation of DDR3 Shared Storage Switching Architecture for Space-based Switches

作　　者：王雷淘 乔庐峰 续欣 WANG Lei-tao;QIAO Lu-feng;XU Xin(Institute of Communication Engineering,Army Engineering University of PLA,Nanjing Jiangsu 210001,China)

机构地区：[1]陆军工程大学通信工程学院,江苏南京210001

出　　处：《通信技术》2020年第6期1546-1553,共8页Communications Technology

摘　　要：设计并实现了一种基于DDR3的星载路由队列管理器,该设计采用片外DDR3 SDRAM作为数据缓冲区,在减少片内资源消耗的同时,可以有效的对大量业务流进行管理,兼顾了路由器高吞吐率的要求和星载路由器存储资源珍贵的实际情况。同时,在DDR3控制器中提出了一种连续处理多个读请求的设计,保证DDR3在面对大量读写请求时,可以连续进行读写,进一步提高了DDR3的利用率。整个设计在Xilinx Virtex-7 XC7V690T上实现,同时采用ModelSim SE-642019.2进行了行为级的仿真分析。A kind of DDR3 based on-board routing queue manager is designed and implemented.The design uses off-chip DDR3 SDRAM as a data buffer,the manager can effectively manage a large number of traffic flow while reducing the consumption of on-chip resources,taking into account the requirements of high throughput routers and the actual situation of precious on-board router storage resources.At the same time,a design of processing multiple read requests continuously in DDR3 controller is proposed to ensure that DDR3 can continuously read and write in the face of a large number of read and write requests,and further improve the utilization rate of DDR3.The entire design is implemented on Xilinx Virtex-7 XC7V690T,and meanwhile,ModelSim SE-642019.2 is used to conduct behavior-level simulation analysis.

关 键 词：DDR3 队列管理器 共享存储交换结构 FPGA 

分 类 号：TP393[自动化与计算机技术—计算机应用技术] TN915.05[自动化与计算机技术—计算机科学与技术]