基于FPGA的多码率卷积编码器设计与实现  

Design and implementation of multi-rate convolutional encoder based on FPGA

作　　者：陈振林 赵利[1] 黄星 唐俏笑 梁仪庆 CHEN Zhenlin;ZHAO Li;HUANG Xing;TANG Qiaoxiao;LIANG Yiqing(School of Information and Communication,Guilin University of Electronic Technology,Guilin 541004,China)

机构地区：[1]桂林电子科技大学信息与通信学院,广西桂林541000

出　　处：《桂林电子科技大学学报》2020年第1期18-21,共4页Journal of Guilin University of Electronic Technology

基　　金：广西精密导航技术与应用重点实验室基金(DH201705);桂林电子科技大学研究生教育创新计划(2019YCXS035)。

摘　　要：为纠正信号在无线信道中由于噪声和干扰产生的误码,采用具有良好信道纠错能力的卷积编码作为信道编码,设计了一种多码率卷积码的编码方法。给出多码率编码器的MATLAB算法,并利用Verilog HDL硬件描述语言完成多码率卷积编码器的FPGA设计,在Isim软件上实现时序仿真验证,并在Spartan-6系列XC6SLX45CSG324 FPGA芯片上完成了多码率卷积编码器的硬件调试。测试结果表明,多码率卷积编码器可以根据无线信道的状态来选择编码速率,并且能应用于实际项目中。In order to correct the error of the signal due to noise and interference in the wireless channel, convolutional coding with good channel error correction capability is employed as the channel coding. The encoding method of multi-rate convolutional code is described.The MATLAB algorithm of multi-rate encoder is given.The FPGA design of multi-rate convolutional encoder is completed by Verilog HDL hardware description language, and the timing simulation is implemented on Isim software.And hardware debugging of multi-rate convolutional encoder is completed on Spartan-6 series XC6 SLX45 CSG324 FPGA chip. The test results show that the multi-rate convolutional encoder can select the coding rate according to the state of the wireless channel and can be applied to the actual project.

关 键 词：多码率卷积编码 现场可编程阵列 信道编码 

分 类 号：TN914[电子电信—通信与信息系统]