高阶调制编码辅助相位同步设计与实现  

Design and Implementation of Code-Aided Carrier Phase Synchronization for High-Order Modulations

作　　者：史德生 武楠[1] 王华[1] 梁涛 匡镜明[1] SHI De-sheng;WU Nan;WANG Hua;LIANG Tao;KUANG Jing-ming(School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China)

机构地区：[1]北京理工大学信息与电子学院,北京100081

出　　处：《北京理工大学学报》2020年第7期778-783,共6页Transactions of Beijing Institute of Technology

摘　　要：介绍了一种新型信道编码辅助最大似然载波相位同步算法,通过仿真分析了相位同步算法的估计精度以及对系统误码率的影响,提出了一种基于FPGA的嵌入式LDPC编码辅助载波相位同步算法结构,实现了LDPC译码器与相位同步器联合迭代,显著降低了算法的计算复杂度和处理延时.在Xilinx公司Kintex-7系列FPGA平台对上述算法进行了实现,给出了资源的使用情况.硬件测试结果表明,编码辅助相位同步算法的误码率曲线与理想同步下的结果非常接近.考虑到数据辅助相位同步插入导频引入的信噪比损失,编码辅助相位同步算法可获得约0.7~0.9 dB的信噪比增益.In this paper,a novel code-aided maximum-likelihood(ML)carrier phase synchronization algorithm was introduced.The mean square error(MSE)of the phase estimation and the impact to the bit error rate(BER)performances were evaluated via simulations.An embedded structure of LDPC code-aided carrier phase synchronization algorithm was proposed based on FPGA to enable joint iteration between phase synchronization and decoding,to reducing the complexity and delay of the algorithm.The algorithm was implemented based on Xilinx Kintex-7 FPGA platform.The test results show that the BER performances of the proposed algorithm are very close to that of the ideal synchronization scenarios.The proposed algorithm outperforms the data-aided algorithm,it can achieve about 0.7~0.9 dB SNR gap.

关 键 词：编码辅助 相位同步 高阶调制 现场可编程门阵列 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]