一种超低功耗的全CMOS基准电压源设计  

An ultra⁃low power consumption full⁃CMOS reference voltage source design

作　　者：王梓淇 王永顺[1] 陈昊 WANG Ziqi;WANG Yongshun;CHEN Hao(School of Electronics and Information Engineering,Lanzhou Jiaotong University,Lanzhou 730070,China)

机构地区：[1]兰州交通大学电子与信息工程学院,甘肃兰州730070

出　　处：《现代电子技术》2020年第16期1-3,8,共4页Modern Electronics Technique

基　　金：国家自然科学基金项目(61366006)。

摘　　要：基于SMIC 0.13μm CMOS工艺,设计一款纳瓦级功耗的全CMOS带隙基准电路。该电路由全CMOS电路实现,避免使用三极管和电阻,实现了节省芯片面积的目的。晶体管工作在三极管区和亚阈值区,大幅降低了功耗。Cadence仿真结果表明:在-20~100℃范围内,温度系数为31 ppm/℃;在电源电压1.2~3.3 V的变化范围内,电源电压漂移系数为0.42%/V。参考电源电压下,电路的电源抑制比(PSRR)达到51.7 dB@100 Hz;室温下,电路总静态电流为22.8 nA,功耗为27.4 nW@1.2 V;该电路可调节性强,适用于低功耗芯片中。A nava⁃level power⁃consumption full⁃CMOS band⁃gap reference circuit is designed based on SMIC 0.13μm CMOS technology.The circuit is realized by full⁃CMOS circuit,and the use of BJTs and resistances has been avoided,and the chip area has been saved.The transistor works in the triode region subthreshold region,which greatly reduces the power consumption.The Cadence simulation results show that the temperature coefficient is 31 ppm/℃when the temperature ranges from-20℃to 100℃.The drift coefficient of power supply voltage is 0.42%/V within its range from 1.2 V to 3.3 V.The circuit′s PSRR can reach 51.7 dB@100 Hz under the reference voltage.At room temperature,the total quiescent current of the circuit is 22.8 nA,and the power consumption is 27.4 nW@1.2 V.This circuit has strong adjustability and is suitable for the low⁃power consumption chip.

关 键 词：全CMOS 带隙基准 基准电压源 电路设计 超低能耗 Cadence仿真 

分 类 号：TN402-34[电子电信—微电子学与固体电子学]