基于复系数-延时信号消除法的锁相环设计  

Design of phase-locked loop based on complex coefficient-delay signal elimination method

作　　者：程勇[1] 张怡龙 毕训训 罗长青 Cheng Yong;Zhang Yilong;Bi Xunxun;Luo Changqing(School of Electric and Control Engineering,Xi’an University of Science and Technology,Xi’an 710054,China)

机构地区：[1]西安科技大学电气与控制工程学院,西安710054

出　　处：《电测与仪表》2020年第15期123-128,共6页Electrical Measurement & Instrumentation

基　　金：陕西省科技厅工业攻关项目(2016GY-064)。

摘　　要：针对电网电压不平衡和谐波污染等复杂工况下传统软件锁相环锁相精度不足等问题,提出一种新型软件锁相环的设计方法。文章分析了传统锁相环的基本原理,对电网频率、锁相环输出频率、相位差对锁相性能的影响进行了研究。通过在两相静止坐标系中施加复系数滤波环节抑制电网高次谐波和负序分量的影响,再利用级联延时信号消除法滤除较低次的特定次谐波。通过仿真结果分析表明所提出锁相环具有良好的动态特性和锁相精度,可以在电网电压不平衡和谐波污染等复杂工况下快速准确完成锁相。Aiming at the problems of insufficient phase locking accuracy of traditional software phase-locked loops (PLL)under complex conditions such as grid voltage imbalance and harmonic pollution,a new software phase-locked loop design method is proposed in this paper. The basic principle of traditional PLL,and the influence of power grid frequency,PLL output frequency and phase difference on PLL performance is analyzed in this paper. By applying a complex coefficient filtering (CCF) link in the two-phase stationary reference frame to suppress the influence of the higher harmonics and negative sequence component of the power grid,the cascaded delay signal cancellation (CDSC) method is used to filter out the lower specified harmonics. The simulation results show that the proposed phase-locked loop has good dynamic characteristics and phase-locked accuracy,which can quickly and accurately complete the phase-locked loop under complex conditions such as voltage imbalance and harmonic pollution.

关 键 词：软件锁相环 复系数滤波 高次谐波 负序分量 级联延时信号消除 

分 类 号：TM935[电气工程—电力电子与电力传动]