高效率PLB2AXI总线桥的设计与验证  

Design and Verification of Efficient PLB2AXI Bus Bridge

作　　者：张浩 魏敬和[1,2] ZHANG Hao;WEI Jinghe(School of Internet of Things Engineering,Jiangnan University,Wuxi,Jiangsu 214122,China;The 58th Research Institute of China Electronics Technology Group Corporation,Wuxi,Jiangsu 214035,China)

机构地区：[1]江南大学物联网工程学院,江苏无锡214122 [2]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《计算机工程》2020年第8期228-234,共7页Computer Engineering

基　　金：国家自然科学基金(61704161)。

摘　　要：为实现片上系统不同IP核之间的协议转换与高效通信,提出一种高效率PLB2AXI总线桥设计方案。利用PLB与AXI高性能总线的带宽优势,通过引入流水线传输和读写重叠传输机制,将PLB总线协议中的地址、数据和控制信号转换为AXI总线协议中的相应信号,从而实现两种总线协议之间的通信。从模块级和FPGA系统级两个方面对PLB2AXI总线桥的功能进行验证,结果表明,该方案设计的总线桥能够正确转换协议,且耗时仅为传统总线桥的54.41%,具有更高的转换传输效率。In order to realize the protocol conversion and efficient communication between different IP cores of the System on Chip(SoC),an efficient PLB2AXI bus bridge design scheme is proposed.By taking advantage of the bandwidth of PLB bus and AXI bus,the address,data and control signals in PLB bus protocol are converted into corresponding signals in AXI bus protocol by introducing the mechanism of pipeline transmission and read-write overlapping transmission,so as to implement the communication between two bus protocols.The functions of PLB2AXI bus bridge is verified at the module level and FPGA system level.The results show that the master cable-bridge of this scheme can converse protocol correctly,and time consuming is only 54.41%of that of the traditional master cable-bridge,so it has a higher conversion and transmission efficiency.

关 键 词：总线桥 片上系统 流水线传输 读写重叠 现场可编程门阵列 

分 类 号：TN402[电子电信—微电子学与固体电子学]