2.56GHz低抖动CMOS集成锁相环的设计  

Design of 2.56 GHz low jitter CMOS integrated phase-locked loop

作　　者：徐安洋 郭迪 孙向明 XU An-yang;GUO Di;SUN Xiang-ming(Institute of Physical Science and Technology,Silicon Pixel Laboratory,Central China Normal University,Wuhan 430079,China)

机构地区：[1]华中师范大学物理科学与技术学院硅像素实验室,湖北武汉430079

出　　处：《电子设计工程》2020年第16期188-193,共6页Electronic Design Engineering

摘　　要：设计了一种基于TowerJazz 180 nm CMOS工艺的低抖动集成锁相环芯片。分别从鉴频鉴相器(PFD)、电荷泵(CP)、压控振荡器(VCO)、环路滤波器(LPF)等多个环路模块分析介绍了减小输出时钟抖动的方法和具体电路实现。采用Cadence仿真软件对整个电路进行仿真,后仿真结果表明该锁相环芯片性能指标良好:工作电压1.8 V,调频范围为1.24~2.95 GHz,输出时钟中心频率为2.56 GHz,锁定时间小于2μs,相位抖动约为1.7 ps。A low-jitter integrated phase-locked loop chip based on TowerJazz 180 nm CMOS technology is designed.The method of reducing the output clock jitter and the specific circuit implementation are introduced from the analysis of multiple modules such as phase frequency detector(PFD),charge pump(CP),voltage controlled oscillator(VCO)and loop low pass filter(LPF).The whole circuit is simulated by Cadence simulation software.The post-simulation results show that the performance of the phase-locked loop chip is good:the operating voltage is 1.8 V,the frequency range is 1.24~2.95 GHz,the output clock center frequency is 2.56 GHz,the locking time is less than 2μs,and the phase jitter is about 1.7 ps.

关 键 词：集成电路 压控振荡器 锁相环 相位抖动 

分 类 号：TN365[电子电信—物理电子学]