基于Cadence CHI和IVD VIP的多核SoC系统数据一致性验证  

Multi-core SoC based on Cadence CHI and IVD VIP system data coherence verification

作　　者：范君健 晁张虎 杨庆娜 刘琪 朱红 单建旗 Fan Junjian;Chao Zhanghu;Yang Qingna;Liu Qi;Zhu Hong;Shan Jianqi(Tianjin Phytium Technology Co.,Ltd.,Tianjin 102209,China;Cadence,Shenzhen 518040,China)

机构地区：[1]天津飞腾信息技术有限公司,天津102209 [2]Cadence,广东深圳518040

出　　处：《电子技术应用》2020年第8期72-76,共5页Application of Electronic Technique

摘　　要：在多核的SoC系统中,不同的处理器核对内存空间和设备空间进行着大量的数据读写操作,维护Cache一致性面临严峻挑战。集中于控制流方面的验证环境搭建已非常复杂,而包含数据正确性检查的验证由于控制流程复杂、数据量大等问题而更加困难。针对这一问题,基于Cadence公司提供CHI VIP、AXI VIP和IVD VIP,实现多核环境下的系统级数据一致性验证。搭建的验证平台中采用CHI VIP通过笔者开发的CHI协议转换桥发出访存请求,使用AXI VIP收集到达主存的数据,由IVD VIP对CHI端口的请求数据与AXI端口的访存数据进行实时分析比对,实现在较高抽象层次上的激励产生和响应检查。该验证平台能够在子系统级及系统级进行数据一致性验证,具有验证环境搭建快速和功能点覆盖完备的优点。In a multi-core SoC system,different processor cores perform a large amount of data read and write operations on memory space and device space.Maintaining cache coherence is facing severe challenges.The verification environment focused on the control flow has been very complicated,and the verification including data correctness check is more difficult due to the complicated control process and large amount of data.In response to this problem,this paper is based on Cadence CHI VIP,AXI VIP and IVD VIP to achieve system-level data coherence verification in a multi-core environment.In this paper,CHI VIP is used to issue a memory access request through the CHI protocol conversion bridge developed by the author,and AXI VIP is used to collect data that arrives in the main memory,real-time analysis and comparison of the request data of the CHI port and the access data of the AXI port by the IVD VIP,to realize stimulus generation and response inspection at a higher level of abstraction.The verification platform can perform data consistency verification at the subsystem level and system level,and has the advantages of rapid verification environment construction and complete coverage of function points.

关 键 词：CACHE一致性 子系统级验证 VIP 模块化验证 

分 类 号：TN409[电子电信—微电子学与固体电子学]