以太网IP核的FPGA验证  

FPGA Verification of Ethernet IP Core

作　　者：蔡玉辉 CAI Yuhui(The 47th Institute of China Electronics Technology Group Corporation,Shenyang 110032,China)

机构地区：[1]中国电子科技集团公司第四十七研究所,沈阳110032

出　　处：《微处理机》2020年第4期30-32,共3页Microprocessors

摘　　要：随着智能互联设备的多元化,具有以太网功能的SoC芯片得到广泛应用。片上系统开发验证技术中,FPGA原型验证是SoC芯片功能验证的有效途径,可以在设计前期及时发现设计中存在的问题。从硬件平台和软件平台两方面对基于FPGA的以太网IP核验证系统展开研究。硬件平台采用母板与子板相结合的方式,通过FMC-HPC连接,将以太网PHY、JTAG调试接口等功能集成于子板,增加硬件平台设计的灵活性。软件平台主要采用基于轻量级的LWIP协议,以有效减少代码尺寸。以此设计出的软硬件协同验证平台,可以有效缩短以太网IP核开发验证周期,降低SoC芯片的开发成本,提高产品的竞争力。With the diversification of intelligent interconnected devices, SoC with Ethernet function has been widely used. In SoC verification technology, FPGA prototyping verification is an effective way,which can timely find the problems existing in the design at the early stage. The verification system of Ethernet IP core based on FPGA is studied from hardware and software platform. The hardware platform combines motherboard with daughter board, and integrates Ethernet PHY, JTAG debugging interface and other functions on the daughter board through FMC-HPC connection, which increases the flexibility of hardware platform design. The software platform mainly adopts LWIP protocol based on lightweight to effectively reduce the code size. The software and hardware co-verification platform designed in this way can effectively shorten the development verification cycle of Ethernet IP core, reduce the development cost of SoC chip and improve the competitiveness of products.

关 键 词：以太网IP核 SOC验证 软硬件协同验证 FPGA验证 

分 类 号：TN492[电子电信—微电子学与固体电子学]