An LFSR-based address generator using optimized address partition for low power memory BIST  

基于改进型LFSR的低功耗MBIST地址生成器

作　　者：YU Zhi-guo LI Qing-qing FENG Yang GU Xiao-feng 虞致国;李青青;冯洋;顾晓峰(江南大学电子工程系,江苏无锡214122;江南大学物联网技术应用教育部工程研究中心,江苏无锡214122)

机构地区：[1]Department of Electronic Engineering,Jiangnan University,Wuxi 214122,China [2]Engineering Research Center of IoT Technology Applications of Ministry of Education,Jiangnan University,Wuxi 214122,China

出　　处：《Journal of Measurement Science and Instrumentation》2020年第3期205-210,共6页测试科学与仪器（英文版）

基　　金：Foundation items:Fundamental Research Funds for the Central Universities(No.JUSRP51510);Primary Research&Development Plan of Jiangsu Province(No.BE2019003-2)。

摘　　要：Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback shift register(LFSR)is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test(MBIST).The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals.An address generator circuit for MBIST of 64 k×32 static random access memory(SRAM)is designed to illustrate the proposed scheme.Experimental results show that when the address bus size is 16 bits,compared with the traditional LFSR,the proposed LFSR can reduce the switching activity and dynamic power by 71.1%and 68.2%,respectively,with low area overhead.

关 键 词：address sequence linear feedback shift register(LFSR) memory built-in self-test(MBIST) address generator switching activity 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]