基于Verilog HDL的并行序列检测器设计  

Serial Detector of Binary Sequence Based on Verilog HDL

作　　者：李红科 王庆春 Li Hongke;Wang Qingchun(Ankang University,Ankang Shaanxi,725000)

机构地区：[1]安康学院电子与信息工程学院,陕西安康725000

出　　处：《电子测试》2020年第17期23-25,8,共4页Electronic Test

摘　　要：Verilog HDL是目前世界上应用最广泛硬件描述语言之一,它的最大优点是设计与工艺分离,设计者在电路设计时可以不必过多考虑工艺实现的具体细节,只需根据系统设计要求,实加不同约束条件,即可设计出实际电路。本文应用Verilog HDL硬件描述语言设计并行序列检测器,当输入并行序列连续出现“10010”时输出高电平,并与常见的序列检测器设计方法比较,设计算法完善,包括所有出现的状态,应用Modelsim se6.5进行功能仿真验证,经过仿真验证,设计正确。Verilog HDL is one of the most widely used hardware description languages in the world.Its biggest advantage is the separation of design and process.Designers can need not too much consider when circuit design process implementation details,just based on the system design requirements,with different constraint conditions,to design a practical circuit.Using Verilog HDL hardware description language design parallel sequential detector,when there is“10010”input sequence continuous parallel output high level,compared with common design method of sequential detector,and design algorithm is perfect,including all the occurrences of the state,the application of Modelsim se6.5 function simulation verification,through simulation,the design is correct.

关 键 词：Verilog HDL 状态机 序列检测器 

分 类 号：TN791[电子电信—电路与系统]